From 448d9fb4310eb8c390020c64af703060ab3545a6 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 22 May 2018 12:51:27 +0200 Subject: src: Use "foo *bar" instead of "foo* bar" Change-Id: Ib2bb6cc80ac2bdc389c60c7ffac4bba937f0fca8 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/26461 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/baytrail/include/soc/gpio.h | 2 +- src/soc/intel/fsp_baytrail/include/soc/gpio.h | 2 +- src/soc/nvidia/tegra210/clock.c | 2 +- src/soc/nvidia/tegra210/include/soc/clock.h | 3 ++- 4 files changed, 5 insertions(+), 4 deletions(-) (limited to 'src/soc') diff --git a/src/soc/intel/baytrail/include/soc/gpio.h b/src/soc/intel/baytrail/include/soc/gpio.h index 0e0395a536..580c4eb80b 100644 --- a/src/soc/intel/baytrail/include/soc/gpio.h +++ b/src/soc/intel/baytrail/include/soc/gpio.h @@ -366,7 +366,7 @@ struct soc_gpio_config { /* Description of GPIO 'bank' ex. {ncore, score. ssus} */ struct gpio_bank { const int gpio_count; - const u8* gpio_to_pad; + const u8 *gpio_to_pad; const int legacy_base; const unsigned long pad_base; const u8 has_wake_en :1; diff --git a/src/soc/intel/fsp_baytrail/include/soc/gpio.h b/src/soc/intel/fsp_baytrail/include/soc/gpio.h index 02c226b1d7..7c81151b51 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/gpio.h +++ b/src/soc/intel/fsp_baytrail/include/soc/gpio.h @@ -342,7 +342,7 @@ struct soc_gpio_config { /* Description of GPIO 'bank' ex. {ncore, score. ssus} */ struct gpio_bank { const int gpio_count; - const u8* gpio_to_pad; + const u8 *gpio_to_pad; const int legacy_base; const unsigned long pad_base; const u8 has_wake_en :1; diff --git a/src/soc/nvidia/tegra210/clock.c b/src/soc/nvidia/tegra210/clock.c index 277ba27050..51cfc8b2c8 100644 --- a/src/soc/nvidia/tegra210/clock.c +++ b/src/soc/nvidia/tegra210/clock.c @@ -646,7 +646,7 @@ void clock_init(void) graphics_pll(); } -void clock_grp_enable_clear_reset(u32 val, u32* clk_enb_set_reg, +void clock_grp_enable_clear_reset(u32 val, u32 *clk_enb_set_reg, u32 *rst_dev_clr_reg) { write32(clk_enb_set_reg, val); diff --git a/src/soc/nvidia/tegra210/include/soc/clock.h b/src/soc/nvidia/tegra210/include/soc/clock.h index f3a63c8e5e..50d72603ee 100644 --- a/src/soc/nvidia/tegra210/include/soc/clock.h +++ b/src/soc/nvidia/tegra210/include/soc/clock.h @@ -433,7 +433,8 @@ void clock_disable_regs(u32 bits[DEV_CONFIG_BLOCKS]); void clock_set_reset_regs(u32 bits[DEV_CONFIG_BLOCKS]); void clock_clr_reset_regs(u32 bits[DEV_CONFIG_BLOCKS]); void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x, u32 y); -void clock_grp_enable_clear_reset(u32 val, u32* clk_enb_set_reg, u32* rst_dev_clr_reg); +void clock_grp_enable_clear_reset(u32 val, u32 *clk_enb_set_reg, + u32 *rst_dev_clr_reg); void clock_reset_l(u32 l); void clock_reset_h(u32 h); void clock_reset_u(u32 u); -- cgit v1.2.3