From 447233ce8c25863c2236d0b208bff7f63cd738fb Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Sun, 22 Nov 2020 15:16:12 +0530 Subject: soc/intel/alderlake: Update UART0 GPIO as per latest schematics UART0_RX: C8 -> H10 UART0_TX: C9 -> H11 GPIO PIN Mode: NF1 -> NF2 Change-Id: I7a193b67e22258ff600679f27955a37480ed3f0d Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/47847 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/alderlake/uart.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/soc') diff --git a/src/soc/intel/alderlake/uart.c b/src/soc/intel/alderlake/uart.c index cdbf8ec123..a3bdc4a3ba 100644 --- a/src/soc/intel/alderlake/uart.c +++ b/src/soc/intel/alderlake/uart.c @@ -21,8 +21,8 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = { { .console_index = 0, .gpios = { - PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0 RX */ - PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0 TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* UART0 RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* UART0 TX */ }, }, { -- cgit v1.2.3