From 40e1cce7e1b62f5c4152664325776453275f6d4e Mon Sep 17 00:00:00 2001
From: Scott Chao <Scott_Chao@wistron.com>
Date: Tue, 21 Feb 2023 11:34:35 +0800
Subject: soc/intel/alderlake: Add UWES ASL into xhci.asl

Align support for enable wake-on-usb attach/detach as was
introduced in Cannon Lake in commit 811284125f0a
("soc/intel/cannonlake: Add UWES ASL into xhci.asl").

 This adds the USB Wake Enable Setup (UWES) ASL blocks
 required to inform the OS about plug wake events bits
 being set in the PORTSCN register configured by devicetree.

BUG=b:230398487
BRANCH=none
TEST=Verify USB-A device could wake up Moli.

Signed-off-by: Scott Chao <Scott_Chao@wistron.com>
Change-Id: Icbc427a89413f5fe3a4a533135cc2c39349a9580
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73173
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
---
 src/soc/intel/alderlake/acpi/xhci.asl     | 73 +++++++++++++++++++++++++++++++
 src/soc/intel/alderlake/include/soc/usb.h |  6 +++
 2 files changed, 79 insertions(+)

(limited to 'src/soc')

diff --git a/src/soc/intel/alderlake/acpi/xhci.asl b/src/soc/intel/alderlake/acpi/xhci.asl
index 3ccc22eb91..465f0aa0b1 100644
--- a/src/soc/intel/alderlake/acpi/xhci.asl
+++ b/src/soc/intel/alderlake/acpi/xhci.asl
@@ -2,6 +2,65 @@
 
 #include <soc/gpe.h>
 
+#define PORTSCN_OFFSET 0x480
+#define PORTSCXUSB3_OFFSET 0x540
+
+#define WAKE_ON_CONNECT_DISCONNECT_ENABLE 0x6000000
+/*
+ * And port status/control reg with RO and RWS bits
+ * RO bits: 0, 2:3, 10:13, 24, 28:30
+ * RWS bits: 5:9, 14:16, 25:27
+ */
+#define RO_BITS_OFF_MASK ~0x80FE0012
+
+/*
+ * USB Port Wake Enable (UPWE) on usb attach/detach
+ * Arg0 - Port Number
+ * Arg1 - Port 1 Status and control offset
+ * Arg2 - xHCI Memory-mapped address
+ */
+Method (UPWE, 3, Serialized)
+{
+	Local0 = Arg1 + ((Arg0 - 1) * 0x10)
+
+	/* Map ((XMEM << 16) + Local0 in PSCR */
+	OperationRegion (PSCR, SystemMemory, (Arg2 << 16) + Local0, 0x10)
+	Field (PSCR, DWordAcc, NoLock, Preserve)
+	{
+		PSCT, 32,
+	}
+	Local0 = PSCT
+
+	Local0 &= RO_BITS_OFF_MASK
+	/* Set WCE and WDE bits */
+	Local0 |= WAKE_ON_CONNECT_DISCONNECT_ENABLE
+	PSCT = Local0
+}
+
+/*
+ * USB Wake Enable Setup (UWES)
+ * Arg0 - Port enable bitmap
+ * Arg1 - Port 1 Status and control offset
+ * Arg2 - xHCI Memory-mapped address
+ */
+Method (UWES, 3, Serialized)
+{
+	Local0 = Arg0
+
+	While (1) {
+		FindSetRightBit (Local0, Local1)
+		If (Local1 == 0) {
+			Break
+		}
+		UPWE (Local1, Arg1, Arg2)
+		/*
+		 * Clear the lowest set bit in Local0 since it was
+		 * processed.
+		 */
+		Local0 &= (Local0 - 1)
+	}
+}
+
 /* XHCI Controller 0:14.0 */
 
 Device (XHCI)
@@ -10,6 +69,20 @@ Device (XHCI)
 
 	Name (_PRW, Package () { GPE0_PME_B0, 3 })
 
+	OperationRegion (XPRT, PCI_Config, 0x00, 0x100)
+	Field (XPRT, AnyAcc, NoLock, Preserve)
+	{
+		Offset (0x10),
+		, 16,
+		XMEM, 16,	/* MEM_BASE */
+	}
+
+	Method (_DSW, 3)
+	{
+		UWES ((\U2WE & 0xFFF), PORTSCN_OFFSET, XMEM)
+		UWES ((\U3WE & 0x3F ), PORTSCXUSB3_OFFSET, XMEM)
+	}
+
 	Name (_S3D, 3)	/* D3 supported in S3 */
 	Name (_S0W, 3)	/* D3 can wake device in S0 */
 	Name (_S3W, 3)	/* D3 can wake system from S3 */
diff --git a/src/soc/intel/alderlake/include/soc/usb.h b/src/soc/intel/alderlake/include/soc/usb.h
index 0eb616055c..2a701c8cc2 100644
--- a/src/soc/intel/alderlake/include/soc/usb.h
+++ b/src/soc/intel/alderlake/include/soc/usb.h
@@ -163,5 +163,11 @@ struct tcss_port_config {
 	.ocpin            = (pin), \
 }
 
+/*
+ * Set bit corresponding to USB port in wake enable bitmap. Bit 0 corresponds
+ * to Port 1, Bit n corresponds to Port (n+1). This bitmap is later used to
+ * decide what ports need to set PORTSCN/PORTSCXUSB3 register bits.
+ */
+#define USB_PORT_WAKE_ENABLE(x)		(1 << ((x) - 1))
 
 #endif
-- 
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