From 400ce55566caa541304b2483e61bcc2df941998c Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Fri, 12 Oct 2018 10:54:30 +0200 Subject: cpu/amd: Use common AMD's MSR Phase 1. Due to the size of the effort, this CL is broken into several phases. Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/29065 Tested-by: build bot (Jenkins) Reviewed-by: Richard Spiegel --- src/soc/amd/stoneyridge/bootblock/bootblock.c | 1 + src/soc/amd/stoneyridge/cpu.c | 6 +++--- src/soc/amd/stoneyridge/finalize.c | 6 +++--- src/soc/amd/stoneyridge/mca.c | 12 ++++++------ src/soc/amd/stoneyridge/northbridge.c | 1 + src/soc/amd/stoneyridge/ramtop.c | 6 +++--- src/soc/amd/stoneyridge/tsc_freq.c | 2 +- 7 files changed, 18 insertions(+), 16 deletions(-) (limited to 'src/soc') diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c index 479e0fc9f2..e9a5bd6116 100644 --- a/src/soc/amd/stoneyridge/bootblock/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 92b2950ad3..c140fca7db 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -18,8 +18,8 @@ #include #include #include +#include #include -#include #include #include #include @@ -89,10 +89,10 @@ static void relocation_handler(int cpu, uintptr_t curr_smbase, tseg_base.lo = relo_attrs.tseg_base; tseg_base.hi = 0; - wrmsr(MSR_TSEG_BASE, tseg_base); + wrmsr(SMM_ADDR_MSR, tseg_base); tseg_mask.lo = relo_attrs.tseg_mask; tseg_mask.hi = ((1 << (cpu_phys_address_size() - 32)) - 1); - wrmsr(MSR_SMM_MASK, tseg_mask); + wrmsr(SMM_MASK_MSR, tseg_mask); smm_state = (void *)(SMM_AMD64_SAVE_STATE_OFFSET + curr_smbase); smm_state->smbase = staggered_smbase; } diff --git a/src/soc/amd/stoneyridge/finalize.c b/src/soc/amd/stoneyridge/finalize.c index 21d203cdd2..45e659504b 100644 --- a/src/soc/amd/stoneyridge/finalize.c +++ b/src/soc/amd/stoneyridge/finalize.c @@ -15,7 +15,7 @@ #include #include -#include +#include #include #include #include @@ -30,9 +30,9 @@ static void per_core_finalize(void *unused) return; if (IS_ENABLED(CONFIG_SMM_TSEG)) { - mask = rdmsr(MSR_SMM_MASK); + mask = rdmsr(SMM_MASK_MSR); mask.lo |= SMM_TSEG_VALID; - wrmsr(MSR_SMM_MASK, mask); + wrmsr(SMM_MASK_MSR, mask); } hwcr.lo |= SMM_LOCK; diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c index df2b9611bf..13e626e397 100644 --- a/src/soc/amd/stoneyridge/mca.c +++ b/src/soc/amd/stoneyridge/mca.c @@ -133,11 +133,11 @@ static void build_bert_mca_error(struct mca_bank *mci) if (!chk) goto failed; - ctx = cper_new_ia32x64_context_msr(status, x86_sec, MCG_CAP, 3); + ctx = cper_new_ia32x64_context_msr(status, x86_sec, IA32_MCG_CAP, 3); if (!ctx) goto failed; ctx = cper_new_ia32x64_context_msr(status, x86_sec, - MC0_CTL + (mci->bank * 4), 4); + IA32_MC0_CTL + (mci->bank * 4), 4); if (!ctx) goto failed; ctx = cper_new_ia32x64_context_msr(status, x86_sec, @@ -169,7 +169,7 @@ void check_mca(void) struct mca_bank mci; int num_banks; - cap = rdmsr(MCG_CAP); + cap = rdmsr(IA32_MCG_CAP); num_banks = cap.lo & MCA_BANKS_MASK; if (is_warm_reset()) { @@ -177,7 +177,7 @@ void check_mca(void) if (i == 3) /* Reserved in Family 15h */ continue; - mci.sts = rdmsr(MC0_STATUS + (i * 4)); + mci.sts = rdmsr(IA32_MC0_STATUS + (i * 4)); if (mci.sts.hi || mci.sts.lo) { int core = cpuid_ebx(1) >> 24; @@ -192,7 +192,7 @@ void check_mca(void) mci.misc = rdmsr(MC0_MISC + (i * 4)); printk(BIOS_WARNING, " MC%d_MISC = %08x_%08x\n", i, mci.misc.hi, mci.misc.lo); - mci.ctl = rdmsr(MC0_CTL + (i * 4)); + mci.ctl = rdmsr(IA32_MC0_CTL + (i * 4)); printk(BIOS_WARNING, " MC%d_CTL = %08x_%08x\n", i, mci.ctl.hi, mci.ctl.lo); mci.cmask = rdmsr(MC0_CTL_MASK + i); @@ -211,5 +211,5 @@ void check_mca(void) mci.sts.lo = 0; mci.sts.hi = 0; for (i = 0 ; i < num_banks ; i++) - wrmsr(MC0_STATUS + (i * 4), mci.sts); + wrmsr(IA32_MC0_STATUS + (i * 4), mci.sts); } diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 95c2a073cb..a2ae52c09e 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c index 72db8ec7e1..7439ab41a5 100644 --- a/src/soc/amd/stoneyridge/ramtop.c +++ b/src/soc/amd/stoneyridge/ramtop.c @@ -19,8 +19,8 @@ #include #include #include +#include #include -#include #include #include #include @@ -102,7 +102,7 @@ void smm_region_info(void **start, size_t *size) static void clear_tvalid(void) { msr_t hwcr = rdmsr(HWCR_MSR); - msr_t mask = rdmsr(MSR_SMM_MASK); + msr_t mask = rdmsr(SMM_MASK_MSR); int tvalid = !!(mask.lo & SMM_TSEG_VALID); if (hwcr.lo & SMM_LOCK) { @@ -114,7 +114,7 @@ static void clear_tvalid(void) } mask.lo &= ~SMM_TSEG_VALID; - wrmsr(MSR_SMM_MASK, mask); + wrmsr(SMM_MASK_MSR, mask); } int smm_subregion(int sub, void **start, size_t *size) diff --git a/src/soc/amd/stoneyridge/tsc_freq.c b/src/soc/amd/stoneyridge/tsc_freq.c index a8ed7c6a4c..89b0a7866e 100644 --- a/src/soc/amd/stoneyridge/tsc_freq.c +++ b/src/soc/amd/stoneyridge/tsc_freq.c @@ -17,8 +17,8 @@ #include #include +#include #include -#include #include #include #include -- cgit v1.2.3