From 3e1943ec46d04aff01c7fc755ac371e33e7a2dcb Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Thu, 6 May 2021 16:08:09 -0600 Subject: soc/amd/cezanne: Force resets to be cold Cezanne must use cold resets. Change the warm reset request to always set TOGGLE_ALL_PWR_GOOD. And, since the bit is sticky across power cycles, set it early for good measure. BUG=b:184281092 TEST=Majolica successfully resets using 0xcf9 Signed-off-by: Marshall Dawson Change-Id: I7d4ca5665335b20100a5c802d12d79c0d0597ad9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52982 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/amd/cezanne/fch.c | 6 ++++++ src/soc/amd/cezanne/reset.c | 8 ++++---- 2 files changed, 10 insertions(+), 4 deletions(-) (limited to 'src/soc') diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c index 028ffec17b..f02d1acec5 100644 --- a/src/soc/amd/cezanne/fch.c +++ b/src/soc/amd/cezanne/fch.c @@ -113,8 +113,14 @@ static void fch_init_acpi_ports(void) PM_ACPI_TIMER_EN_EN); } +static void fch_init_resets(void) +{ + pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD); +} + void fch_init(void *chip_info) { + fch_init_resets(); i2c_soc_init(); fch_init_acpi_ports(); diff --git a/src/soc/amd/cezanne/reset.c b/src/soc/amd/cezanne/reset.c index aae76bf4c6..d97f79eb20 100644 --- a/src/soc/amd/cezanne/reset.c +++ b/src/soc/amd/cezanne/reset.c @@ -7,6 +7,7 @@ #include #include +/* TODO: is NCP_ERR still valid? It appears reserved and always 0xff. b/184281092 */ void set_warm_reset_flag(void) { uint8_t ncp = inw(NCP_ERR); @@ -29,14 +30,13 @@ void do_cold_reset(void) void do_warm_reset(void) { - set_warm_reset_flag(); - - /* Assert reset signals only. */ + /* Warm resets are not supported and must be executed as cold */ + pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | + TOGGLE_ALL_PWR_GOOD); outb(RST_CPU | SYS_RST, RST_CNT); } void do_board_reset(void) { - /* TODO: Would a warm_reset() suffice? */ do_cold_reset(); } -- cgit v1.2.3