From 3b037989537bd45350a41c5ae523f51aa44b492f Mon Sep 17 00:00:00 2001 From: Meera Ravindranath Date: Thu, 11 Nov 2021 18:02:13 +0530 Subject: soc/intel/alderlake: Disable VT-d for early silicons VT-d needs to disabled for early silicons as it results in a CPU hard hang. BUG=b:197177091 Test=Boot brya to OS with no hang Signed-off-by: Meera Ravindranath Change-Id: I0b9b76b6527d8b80777cb7588ce6b12282af7882 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59191 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer Reviewed-by: Tim Wawrzynczak Reviewed-by: EricR Lai --- src/soc/intel/alderlake/romstage/fsp_params.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'src/soc') diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index be71a02c0a..121251e7de 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -259,6 +260,14 @@ static void fill_fspm_usb4_params(FSP_M_CONFIG *m_cfg, static void fill_fspm_vtd_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_alderlake_config *config) { + const uint32_t cpuid = cpu_get_cpuid(); + + /* Disable VT-d for early silicon steppings as it results in a CPU hard hang */ + if (cpuid == CPUID_ALDERLAKE_A0 || cpuid == CPUID_ALDERLAKE_A1) { + m_cfg->VtdDisable = 1; + return; + } + m_cfg->VtdBaseAddress[VTD_GFX] = GFXVT_BASE_ADDRESS; m_cfg->VtdBaseAddress[VTD_IPU] = IPUVT_BASE_ADDRESS; m_cfg->VtdBaseAddress[VTD_VTVCO] = VTVC0_BASE_ADDRESS; -- cgit v1.2.3