From 3aa34a8167c0e0f0ecdb823b5ab1de5c3b171f06 Mon Sep 17 00:00:00 2001
From: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Date: Mon, 4 Apr 2016 10:47:49 -0700
Subject: soc/apollolake/lpc: Allow configuring SERIRQ via devicetree

Every other SOC uses a CONFIG_* flag to enable or disable SERIRQ
continuous mode. Why they do that is beyond me, but the way we
implement it on apollolake is via devicetree.

Change-Id: I6e05758e5e264c6b0015467dd25add3bffe2b040
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/14586
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/soc/intel/apollolake/chip.h | 10 ++++++++++
 src/soc/intel/apollolake/lpc.c  | 24 ++++++++++++++++++++++++
 2 files changed, 34 insertions(+)

(limited to 'src/soc')

diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index 9d2bc46d61..d74084ebff 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -20,6 +20,13 @@
 
 #define CLKREQ_DISABLED		0xf
 
+/* Serial IRQ control. SERIRQ_QUIET is the default (0). */
+enum serirq_mode {
+	SERIRQ_QUIET,
+	SERIRQ_CONTINUOUS,
+	SERIRQ_OFF,
+};
+
 struct soc_intel_apollolake_config {
 	/*
 	 * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has
@@ -32,6 +39,9 @@ struct soc_intel_apollolake_config {
 	uint8_t pcie_rp3_clkreq_pin;
 	uint8_t pcie_rp4_clkreq_pin;
 	uint8_t pcie_rp5_clkreq_pin;
+
+	/* Configure serial IRQ (SERIRQ) line. */
+	enum serirq_mode serirq_mode;
 };
 
 #endif	/* _SOC_APOLLOLAKE_CHIP_H_ */
diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c
index 5b552d8491..ce9f00173f 100644
--- a/src/soc/intel/apollolake/lpc.c
+++ b/src/soc/intel/apollolake/lpc.c
@@ -15,6 +15,7 @@
  * GNU General Public License for more details.
  */
 
+#include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
@@ -22,6 +23,8 @@
 #include <soc/lpc.h>
 #include <soc/pci_ids.h>
 
+#include "chip.h"
+
 /*
  * SCOPE:
  * The purpose of this driver is to eliminate manual resource allocation for
@@ -40,6 +43,26 @@
  * opens up IO and memory windows as needed.
  */
 
+static void lpc_init(struct device *dev)
+{
+	uint8_t scnt;
+	struct soc_intel_apollolake_config *cfg;
+
+	cfg = dev->chip_info;
+	if (!cfg) {
+		printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
+		return;
+	}
+
+	scnt = pci_read_config8(dev, REG_SERIRQ_CTL);
+	scnt &= ~(SCNT_EN | SCNT_MODE);
+	if (cfg->serirq_mode == SERIRQ_QUIET)
+		scnt |= SCNT_EN;
+	else if (cfg->serirq_mode == SERIRQ_CONTINUOUS);
+		scnt |= SCNT_EN | SCNT_MODE;
+	pci_write_config8(dev, REG_SERIRQ_CTL, scnt);
+}
+
 static void soc_lpc_add_io_resources(device_t dev)
 {
 	struct resource *res;
@@ -116,6 +139,7 @@ static struct device_operations device_ops = {
 	.enable_resources = &pci_dev_enable_resources,
 	.write_acpi_tables = southbridge_write_acpi_tables,
 	.acpi_inject_dsdt_generator = southbridge_inject_dsdt,
+	.init = lpc_init,
 	.scan_bus = scan_lpc_bus,
 };
 
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