From 2eec87a553ec09ac1bc0ecfc43653ce4affd1ff0 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 20 Apr 2022 12:49:42 +0530 Subject: soc/intel/alderlake: Refactor `pmc_lockdown_cfg` function This patch refactors the `pmc_lockdown_cfg()` to remove the helper functions and uses the `setbits32` function to enforce bit locking as applicable. BUG=b:211954778 TEST=Able to build google/redrix with these changes and boot to OS. > localhost ~ # iotools mmio_read32 0xfe0018c4 0x85000000 (bit 31 is set) > localhost ~ # iotools mmio_read32 0xfe001024 0x00062610 (bits 4, 17 and 18 are set) Signed-off-by: Subrata Banik Change-Id: Ic96da4638aa689b5fa47a3356986ca5a0343fe36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63737 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Angel Pons --- src/soc/intel/alderlake/lockdown.c | 44 +++++--------------------------------- 1 file changed, 5 insertions(+), 39 deletions(-) (limited to 'src/soc') diff --git a/src/soc/intel/alderlake/lockdown.c b/src/soc/intel/alderlake/lockdown.c index e9e4b592e8..b0da51ffdd 100644 --- a/src/soc/intel/alderlake/lockdown.c +++ b/src/soc/intel/alderlake/lockdown.c @@ -12,51 +12,17 @@ #include #include -static void pmc_lock_pmsync(void) -{ - uint8_t *pmcbase; - uint32_t pmsyncreg; - - pmcbase = pmc_mmio_regs(); - - pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG); - pmsyncreg |= PCH2CPU_TPR_CFG_LOCK; - write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg); -} - -static void pmc_lock_abase(void) -{ - uint8_t *pmcbase; - uint32_t reg32; - - pmcbase = pmc_mmio_regs(); - - reg32 = read32(pmcbase + GEN_PMCON_B); - reg32 |= (SLP_STR_POL_LOCK | ACPI_BASE_LOCK); - write32(pmcbase + GEN_PMCON_B, reg32); -} - -static void pmc_lock_smi(void) -{ - uint8_t *pmcbase; - uint8_t reg8; - - pmcbase = pmc_mmio_regs(); - - reg8 = read8(pmcbase + GEN_PMCON_B); - reg8 |= SMI_LOCK; - write8(pmcbase + GEN_PMCON_B, reg8); -} - static void pmc_lockdown_cfg(int chipset_lockdown) { + uint8_t *pmcbase = pmc_mmio_regs(); + /* PMSYNC */ - pmc_lock_pmsync(); + setbits32(pmcbase + PMSYNC_TPR_CFG, PCH2CPU_TPR_CFG_LOCK); /* Lock down ABASE and sleep stretching policy */ - pmc_lock_abase(); + setbits32(pmcbase + GEN_PMCON_B, SLP_STR_POL_LOCK | ACPI_BASE_LOCK); if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) - pmc_lock_smi(); + setbits32(pmcbase + GEN_PMCON_B, SMI_LOCK); } void soc_lockdown_config(int chipset_lockdown) -- cgit v1.2.3