From 2e87b28fb6e9ccca2d6bea868c00f50328e0df99 Mon Sep 17 00:00:00 2001 From: Jimmy Zhang Date: Fri, 14 Nov 2014 20:44:40 -0800 Subject: tegra132: Add framebuffer parameters Framebuffer line size and number of lines can have different values than panel's resolution. BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Change-Id: I228f1dd7fafc6577a8e8a987ff31ba73f7a655ed Signed-off-by: Patrick Georgi Original-Commit-Id: 9a4929dc5831076f2f2a5dd2e13f24b3477e197b Original-Change-Id: Iedeef796f02286bb03920413420f8952cf34334a Original-Signed-off-by: Jimmy Zhang Original-Reviewed-on: https://chromium-review.googlesource.com/229915 Original-Tested-by: Jimmy Zhang Original-Reviewed-by: Aaron Durbin Original-Commit-Queue: Aaron Durbin Reviewed-on: http://review.coreboot.org/9520 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/nvidia/tegra132/chip.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'src/soc') diff --git a/src/soc/nvidia/tegra132/chip.h b/src/soc/nvidia/tegra132/chip.h index 35e72d59e6..2468870569 100644 --- a/src/soc/nvidia/tegra132/chip.h +++ b/src/soc/nvidia/tegra132/chip.h @@ -27,7 +27,8 @@ struct soc_nvidia_tegra132_config { uintptr_t spintable_addr; /* - * panel default specification + * panel resolution + * The two parameters below provides dc about panel spec. */ u32 xres; /* the width of H display active area */ u32 yres; /* the height of V display active area */ @@ -45,6 +46,15 @@ struct soc_nvidia_tegra132_config { */ u32 framebuffer_size; + /* + * Framebuffer resolution + * The two parameters below provides dc about framebuffer's sdram size. + * When they are not the same as panel resolution, we need to program + * dc's DDA_INCREMENT and some other registers to resize dc output. + */ + u32 display_xres; + u32 display_yres; + int href_to_sync; /* HSYNC position with respect to line start */ int hsync_width; /* the width of HSYNC pulses */ int hback_porch; /* the distance between HSYNC trailing edge to -- cgit v1.2.3