From 2e4fa0cb589776feb38f3530fc14b57d627670a3 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 13 Jan 2021 03:16:03 +0100 Subject: soc/amd/cezanne: add remaining non-ACPI parts of UART support The ACPI part still needs some more code to be in place, so add that later. TEST=Together with the currently not merged rest of the amdfw patch train applied this results in working serial console in bootblock in Majolica. Change-Id: Ia844e86a80c19026ac5b47a5a1e91c2553ea5cca Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/49378 Reviewed-by: Marshall Dawson Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/amd/cezanne/uart.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) (limited to 'src/soc') diff --git a/src/soc/amd/cezanne/uart.c b/src/soc/amd/cezanne/uart.c index 02a6d22b09..84f7c40078 100644 --- a/src/soc/amd/cezanne/uart.c +++ b/src/soc/amd/cezanne/uart.c @@ -1,8 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include +#include +#include #include #include #include @@ -43,3 +46,35 @@ void set_uart_config(unsigned int idx) program_gpios(uart_info[idx].mux, 2); } + +/* Even though this is called enable, it gets called for both enabled and disabled devices. */ +static void uart_enable(struct device *dev) +{ + unsigned int dev_id; + + switch (dev->path.mmio.addr) { + case APU_UART0_BASE: + dev_id = FCH_AOAC_DEV_UART0; + break; + case APU_UART1_BASE: + dev_id = FCH_AOAC_DEV_UART1; + break; + default: + printk(BIOS_ERR, "%s: Unknown device: %s\n", __func__, dev_path(dev)); + return; + } + + if (dev->enabled) { + power_on_aoac_device(dev_id); + wait_for_aoac_enabled(dev_id); + } else { + power_off_aoac_device(dev_id); + } +} + +struct device_operations cezanne_uart_mmio_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .scan_bus = scan_static_bus, + .enable = uart_enable, +}; -- cgit v1.2.3