From 2e1384aa4790c90737bb082510862661b819ff84 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Fri, 12 Feb 2021 15:49:06 +0100
Subject: soc/amd/cezanne/bootblock: call write_resume_eip in bootblock_c_entry

Change-Id: I0b785abdd56af3bb67e3e36e5e3b40e544f0ca5a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
---
 src/soc/amd/cezanne/bootblock.c | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/soc')

diff --git a/src/soc/amd/cezanne/bootblock.c b/src/soc/amd/cezanne/bootblock.c
index d1479da6f4..2447de64fc 100644
--- a/src/soc/amd/cezanne/bootblock.c
+++ b/src/soc/amd/cezanne/bootblock.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <amdblocks/amd_pci_mmconf.h>
+#include <amdblocks/cpu.h>
 #include <bootblock_common.h>
 #include <console/console.h>
 #include <cpu/amd/mtrr.h>
@@ -88,6 +89,7 @@ static void set_caching(void)
 asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
 {
 	set_caching();
+	write_resume_eip();
 	enable_pci_mmconf();
 
 	/*
-- 
cgit v1.2.3