From 2ba4bfef7ed31ff2950ecd6c7269d4148d652764 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 26 Jul 2022 12:48:39 +0000 Subject: soc/intel/gpio: Add new macro for GPP PAD reset type as `Global Reset` This patch introduces a new macro for GPP PAD reset type as `Global Reset` as documented in Alder Lake EDS doc 630603. BUG=b:213293047 TEST=Able to build Google/Kano with this change. Signed-off-by: Subrata Banik Change-Id: I39428911babc393dd10750801522a00d0b26d3e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66154 Tested-by: build bot (Jenkins) Reviewed-by: Tarun Tuli Reviewed-by: Eric Lai --- src/soc/intel/common/block/include/intelblocks/gpio_defs.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/soc') diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index efa960cf8a..beff0a0f9b 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -45,6 +45,11 @@ #define PAD_CFG0_LOGICAL_RESET_DEEP (1U << 30) #define PAD_CFG0_LOGICAL_RESET_PLTRST (2U << 30) #define PAD_CFG0_LOGICAL_RESET_RSMRST (3U << 30) +/* + * Alder Lake PCH onwards a newer bit field has added + * for GPP as `Global Reset` + */ +#define PAD_CFG0_LOGICAL_RESET_GLBRST (3U << 30) /* * Use the fourth bit in IntSel field to indicate gpio -- cgit v1.2.3