From 298b35923d08747608224bc12d569cce731e5c35 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 14 Sep 2021 12:38:08 +0530 Subject: drivers/intel/fsp2_0: Refactor MultiPhaseSiInit API calling method FspMultiPhaseSiInit API was introduced with FSP 2.2 specification onwards. EnableMultiPhaseSiliconInit is an arch UPD also introduced as part of FSP 2.2 specification to allow calling FspMultiPhaseSiInit API. However, some platforms adhere to the FSP specification but don't have arch UPD structure, for example : JSL, TGL and Xeon-SP. Out of these platforms, TGL supports calling of FspMultiPhaseSiInit API and considered EnableMultiPhaseSiliconInit as a platform-specific UPD rather than an arch UPD to allow calling into FspMultiPhaseSiInit API. It is important to ensure that the UPD setting and the callback for MultiPhaseInit are kept in sync, else it could result in broken behavior e.g. a hang is seen in FSP if EnableMultiPhaseSiliconInit UPD is set to 1 but the FspMultiPhaseSiInit API call is skipped. This patch provides an option for users to choose to bypass calling into MultiPhaseSiInit API and ensures the EnableMultiPhaseSiliconInit UPD is set to its default state as `disable` so that FSP-S don't consider MultiPhaseSiInit API is a mandatory entry point prior to calling other FSP API entry points. List of changes: 1. Add `FSPS_HAS_ARCH_UPD` Kconfig for SoC to select if `FSPS_ARCH_UPD` structure is part of `FSPS_UPD` structure. 2. Drop `soc_fsp_multi_phase_init_is_enable()` from JSL and Xeon-SP SoCs, a SoC override to callout that SoC doesn't support calling MultiPhase Si Init is no longer required. 3. Add `FSPS_USE_MULTI_PHASE_INIT` Kconfig for SoC to specify if SoC users want to enable `EnableMultiPhaseSiliconInit` arch UPD (using `fsp_fill_common_arch_params()`) and execute FspMultiPhaseSiInit() API. 4. Presently selects `FSPS_USE_MULTI_PHASE_INIT` from IA TCSS common code. 5. Add `fsp_is_multi_phase_init_enabled()` that check applicability of MultiPhase Si Init prior calling FspMultiPhaseSiInit() API to honor SoC users' decision. 6. Drop `arch_silicon_init_params()` from SoC as FSP driver (FSP 2.2) would check the applicability of MultiPhase Si Init prior calling FspMultiPhaseSiInit() API. Additionally, selects FSPS_HAS_ARCH_UPD for Alder Lake as Alder Lake FSPS_UPD structure has `FSPS_ARCH_UPD` structure and drops `arch_silicon_init_params()` from SoC `platform_fsp_silicon_init_params_cb()`. Skip EnableMultiPhaseSiliconInit hardcoding for Tiger Lake and uses the fsp_is_multi_phase_init_enabled() function to override EnableMultiPhaseSiliconInit UPD prior calling MultiPhaseSiInit FSP API. TEST=EnableMultiPhaseSiliconInit UPD is getting set or reset based on SoC user selects FSPS_USE_MULTI_PHASE_INIT Kconfig. Change-Id: I019fa8364605f5061d56e2d80b20e1a91857c423 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/56382 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/alderlake/Kconfig | 1 + src/soc/intel/alderlake/fsp_params.c | 8 -------- src/soc/intel/common/block/tcss/Kconfig | 1 + src/soc/intel/jasperlake/fsp_params.c | 6 ------ src/soc/intel/tigerlake/fsp_params.c | 4 ++-- src/soc/intel/xeon_sp/cpx/ramstage.c | 6 ------ 6 files changed, 4 insertions(+), 22 deletions(-) (limited to 'src/soc') diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 0b28938401..915dd3f381 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -24,6 +24,7 @@ config CPU_SPECIFIC_OPTIONS select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW select FSP_M_XIP select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 + select FSPS_HAS_ARCH_UPD select GENERIC_GPIO_LIB select HAVE_FSP_GOP select INTEL_DESCRIPTOR_MODE_CAPABLE diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 107d22e9e4..541a9612d8 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -672,12 +672,6 @@ static void fill_fsps_fivr_params(FSP_S_CONFIG *s_cfg, config->ext_fivr_settings.vnn_icc_max_ma; } -static void arch_silicon_init_params(FSPS_ARCH_UPD *s_arch_cfg) -{ - /* EnableMultiPhaseSiliconInit for running MultiPhaseSiInit */ - s_arch_cfg->EnableMultiPhaseSiliconInit = 1; -} - static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg, struct soc_intel_alderlake_config *config) { @@ -718,10 +712,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { struct soc_intel_alderlake_config *config; FSP_S_CONFIG *s_cfg = &supd->FspsConfig; - FSPS_ARCH_UPD *s_arch_cfg = &supd->FspsArchUpd; config = config_of_soc(); - arch_silicon_init_params(s_arch_cfg); soc_silicon_init_params(s_cfg, config); mainboard_silicon_init_params(s_cfg); } diff --git a/src/soc/intel/common/block/tcss/Kconfig b/src/soc/intel/common/block/tcss/Kconfig index 3eb0931611..2e679138cd 100644 --- a/src/soc/intel/common/block/tcss/Kconfig +++ b/src/soc/intel/common/block/tcss/Kconfig @@ -1,5 +1,6 @@ config SOC_INTEL_COMMON_BLOCK_TCSS def_bool n + select FSPS_USE_MULTI_PHASE_INIT help Sets up USB2/3 port mapping in TCSS MUX and sets MUX to disconnect state diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index 11b146b577..18db9359ce 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -204,12 +204,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) mainboard_silicon_init_params(params); } -/* Disable Multiphase Si init */ -int soc_fsp_multi_phase_init_is_enable(void) -{ - return 0; -} - /* Mainboard GPIO Configuration */ __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) { diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index bb100df633..892363b75c 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -565,8 +565,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) config->PchPmSlpS3MinAssert, config->PchPmSlpAMinAssert, config->PchPmPwrCycDur); - /* EnableMultiPhaseSiliconInit for running MultiPhaseSiInit */ - params->EnableMultiPhaseSiliconInit = 1; + /* Override EnableMultiPhaseSiliconInit prior calling MultiPhaseSiInit */ + params->EnableMultiPhaseSiliconInit = fsp_is_multi_phase_init_enabled(); /* Disable C1 C-state Demotion */ params->C1StateAutoDemotion = 0; diff --git a/src/soc/intel/xeon_sp/cpx/ramstage.c b/src/soc/intel/xeon_sp/cpx/ramstage.c index 1e0ba008c2..cd1b038b52 100644 --- a/src/soc/intel/xeon_sp/cpx/ramstage.c +++ b/src/soc/intel/xeon_sp/cpx/ramstage.c @@ -1,13 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include -int soc_fsp_multi_phase_init_is_enable(void) -{ - return 0; -} - unsigned int smbios_cpu_get_max_speed_mhz(void) { return 3900; -- cgit v1.2.3