From 291758ddbaa004f9ca2326b3d9f6b5e37bc663ec Mon Sep 17 00:00:00 2001 From: Sean Rhodes Date: Thu, 28 Jul 2022 20:50:49 +0100 Subject: soc/intel/apollolake/acpi: Add PCIEXBAR to MCHC The values in this patch were found in the following datasheets: * 334819 (APL) * 336561 (GLK) Signed-off-by: Sean Rhodes Change-Id: I14c5933b9022703c8951da7c6a26eb703258ec37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66230 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/apollolake/acpi/northbridge.asl | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'src/soc') diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl index f8023bed9c..373d6b8ea4 100644 --- a/src/soc/intel/apollolake/acpi/northbridge.asl +++ b/src/soc/intel/apollolake/acpi/northbridge.asl @@ -11,8 +11,12 @@ Device (MCHC) OperationRegion (MCHP, PCI_Config, 0x00, 0x100) Field (MCHP, DWordAcc, NoLock, Preserve) { - Offset(0x60), - MCNF, 32, /* PCI MMCONF base */ + Offset (0x60), /* PCIEXBAR (0:0:0:60) + PXEN, 1, /* Enable */ + PXSZ, 2, /* PCI Express Size */ + , 25, + PXBR, 11, /* PCI Express Base Address */ + Offset (0xA8), TUUD, 64, /* Top of Upper Used Memory */ Offset(0xB4), -- cgit v1.2.3