From 23cc165d6a02020ff408bdcc56a07cd9dc9a2105 Mon Sep 17 00:00:00 2001
From: Mathew King <mathewk@chromium.org>
Date: Wed, 14 Apr 2021 15:29:44 -0600
Subject: soc/amd/cezanne: Add modern standby option to chip config

BUG=b:178728116

Change-Id: I0d09bd4361f5f47360daf750efbc993010804902
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
---
 src/soc/amd/cezanne/chip.h | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'src/soc')

diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h
index 76ecbfa057..b2c346252b 100644
--- a/src/soc/amd/cezanne/chip.h
+++ b/src/soc/amd/cezanne/chip.h
@@ -11,6 +11,9 @@ struct soc_amd_cezanne_config {
 	struct soc_amd_common_config common_config;
 	u8 i2c_scl_reset;
 	struct dw_i2c_bus_config i2c[I2C_CTRLR_COUNT];
+
+	/* Enable S0iX support */
+	bool s0ix_enable;
 };
 
 #endif /* CEZANNE_CHIP_H */
-- 
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