From 21fdd44db037e4751f9793a2fcf4a3646a70fd88 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Mon, 31 Jan 2022 15:29:04 -0700 Subject: soc/amd/cezanne,vc/cezanne: Implement svc_write_postcode This will allow verstage to write post codes. BUG=b:215425753 TEST=Boot guybrush and verify PSP post codes are printed 22-01-31 15:12:03.214 (S3->S0) 22-01-31 15:12:03.214 03 04 0f 0e f0 f1 f2 01 10 a0 a2 <--new Signed-off-by: Raul E Rangel Change-Id: I6ceee8fcb094f462de99c07aef8e96425d9c3270 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61522 Reviewed-by: Kangheui Won Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) --- src/soc/amd/cezanne/psp_verstage/chipset.c | 10 ---------- src/soc/amd/cezanne/psp_verstage/svc.c | 7 +++++++ 2 files changed, 7 insertions(+), 10 deletions(-) (limited to 'src/soc') diff --git a/src/soc/amd/cezanne/psp_verstage/chipset.c b/src/soc/amd/cezanne/psp_verstage/chipset.c index 30f613a492..41d318e0eb 100644 --- a/src/soc/amd/cezanne/psp_verstage/chipset.c +++ b/src/soc/amd/cezanne/psp_verstage/chipset.c @@ -40,13 +40,3 @@ void platform_report_mode(int developer_mode_enabled) else svc_set_platform_boot_mode(CHROME_BOOK_BOOT_MODE_PRODUCTION); } - - -/* Functions below are stub functions for not-yet-implemented PSP features. - * These functions should be replaced with proper implementations later. - */ - -uint32_t svc_write_postcode(uint32_t postcode) -{ - return 0; -} diff --git a/src/soc/amd/cezanne/psp_verstage/svc.c b/src/soc/amd/cezanne/psp_verstage/svc.c index 78f71260a4..12fccc38f7 100644 --- a/src/soc/amd/cezanne/psp_verstage/svc.c +++ b/src/soc/amd/cezanne/psp_verstage/svc.c @@ -140,3 +140,10 @@ uint32_t svc_set_platform_boot_mode(enum chrome_platform_boot_mode boot_mode) SVC_CALL1(SVC_SET_PLATFORM_BOOT_MODE, (uint32_t)boot_mode, retval); return retval; } + +uint32_t svc_write_postcode(uint32_t postcode) +{ + uint32_t retval = 0; + SVC_CALL1(SVC_WRITE_POSTCODE, postcode, retval); + return retval; +} -- cgit v1.2.3