From 1fa72d5fe1d2ac41036c08355c760fb576899347 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Thu, 24 Sep 2020 23:33:34 +0200 Subject: x86: Add a minimal example SoC along with a board The min86 example SoC code along with the example mainboard should serve as a minimal example how a buildable x86 SoC code base can look like. This can serve, for instance, as a basis to add new SoCs to coreboot. Starting with a buildable commit should help with the review of the actual code, and also avoid any regressions when common coreboot code changes. As the example code itself is build-tested, it should advance with coreboot and can't rot like documentation might. It also serves as a check what APIs need to be implemented with the default Kconfig settings. Change-Id: Id76ab15fe77ae3e405c43f9c8677694f178be112 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/45710 Reviewed-by: Tim Wawrzynczak Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/example/Kconfig | 1 + src/soc/example/min86/Kconfig | 25 +++++++++++++++++++++++++ src/soc/example/min86/Makefile.inc | 15 +++++++++++++++ src/soc/example/min86/cache_as_ram.S | 11 +++++++++++ src/soc/example/min86/chip.c | 3 +++ src/soc/example/min86/exit_car.S | 8 ++++++++ src/soc/example/min86/romstage.c | 7 +++++++ src/soc/example/min86/timer.c | 7 +++++++ 8 files changed, 77 insertions(+) create mode 100644 src/soc/example/Kconfig create mode 100644 src/soc/example/min86/Kconfig create mode 100644 src/soc/example/min86/Makefile.inc create mode 100644 src/soc/example/min86/cache_as_ram.S create mode 100644 src/soc/example/min86/chip.c create mode 100644 src/soc/example/min86/exit_car.S create mode 100644 src/soc/example/min86/romstage.c create mode 100644 src/soc/example/min86/timer.c (limited to 'src/soc') diff --git a/src/soc/example/Kconfig b/src/soc/example/Kconfig new file mode 100644 index 0000000000..5bc004aadb --- /dev/null +++ b/src/soc/example/Kconfig @@ -0,0 +1 @@ +source "src/soc/example/*/Kconfig" diff --git a/src/soc/example/min86/Kconfig b/src/soc/example/min86/Kconfig new file mode 100644 index 0000000000..38b23c0dd2 --- /dev/null +++ b/src/soc/example/min86/Kconfig @@ -0,0 +1,25 @@ +config SOC_EXAMPLE_MIN86 + bool + help + This example SoC code along with the example/min86 mainboard + should serve as a minimal example how a buildable x86 SoC code + base can look like. + + This can serve, for instance, as a basis to add new SoCs to + coreboot. Starting with a buildable commit should help with + the review of the actual code, and also avoid any regressions + when common coreboot code changes. + +if SOC_EXAMPLE_MIN86 + +config SOC_SPECIFIC_OPTIONS + def_bool y + select ARCH_ALL_STAGES_X86_32 + select NO_MONOTONIC_TIMER + select NO_MMCONF_SUPPORT + select UNKNOWN_TSC_RATE + +config DCACHE_BSP_STACK_SIZE # required by arch/x86/car.ld + default 0x100 + +endif diff --git a/src/soc/example/min86/Makefile.inc b/src/soc/example/min86/Makefile.inc new file mode 100644 index 0000000000..9c1c7f0331 --- /dev/null +++ b/src/soc/example/min86/Makefile.inc @@ -0,0 +1,15 @@ +ifeq ($(CONFIG_SOC_EXAMPLE_MIN86),y) + +bootblock-y += cache_as_ram.S +bootblock-y += ../../../cpu/intel/car/bootblock.c + +postcar-y += exit_car.S + +romstage-y += romstage.c + +ramstage-y += chip.c +ramstage-y += timer.c + +subdirs-y += ../../../cpu/x86/mtrr + +endif diff --git a/src/soc/example/min86/cache_as_ram.S b/src/soc/example/min86/cache_as_ram.S new file mode 100644 index 0000000000..a350143834 --- /dev/null +++ b/src/soc/example/min86/cache_as_ram.S @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +.global bootblock_pre_c_entry + +.code32 +bootblock_pre_c_entry: + call bootblock_c_entry_bist + +.Lhlt: + hlt + jmp .Lhlt diff --git a/src/soc/example/min86/chip.c b/src/soc/example/min86/chip.c new file mode 100644 index 0000000000..dd09891e3c --- /dev/null +++ b/src/soc/example/min86/chip.c @@ -0,0 +1,3 @@ +#include + +struct chip_operations soc_example_min86_ops = { NULL }; diff --git a/src/soc/example/min86/exit_car.S b/src/soc/example/min86/exit_car.S new file mode 100644 index 0000000000..0f1b227c2d --- /dev/null +++ b/src/soc/example/min86/exit_car.S @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +.global chipset_teardown_car + +.code32 +chipset_teardown_car: + /* Return to caller. */ + jmp *%esp diff --git a/src/soc/example/min86/romstage.c b/src/soc/example/min86/romstage.c new file mode 100644 index 0000000000..91074b2012 --- /dev/null +++ b/src/soc/example/min86/romstage.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +asmlinkage void car_stage_entry(void) +{ +} diff --git a/src/soc/example/min86/timer.c b/src/soc/example/min86/timer.c new file mode 100644 index 0000000000..9054ffd972 --- /dev/null +++ b/src/soc/example/min86/timer.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +void init_timer(void) +{ +} -- cgit v1.2.3