From 1e3b2ce061626e6c5a7d7f89d40a854bac16f3d4 Mon Sep 17 00:00:00 2001
From: Felix Singer <felixsinger@posteo.net>
Date: Mon, 7 Dec 2020 01:28:59 +0100
Subject: soc/intel/cannonlake: Align SATA mode names with soc/skl
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Align the SATA mode names with soc/skl providing a consistent API.

Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains
identical.

Change-Id: I54b48462852d7fe0230dde0c272da3d12365d987
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
---
 src/soc/intel/cannonlake/chip.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/soc')

diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index a084f67b46..70aab92853 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -129,8 +129,8 @@ struct soc_intel_cannonlake_config {
 
 	/* SATA related */
 	enum {
-		Sata_AHCI,
-		Sata_RAID,
+		SATA_AHCI,
+		SATA_RAID,
 	} SataMode;
 
 	/* SATA devslp pad reset configuration */
-- 
cgit v1.2.3