From 1c33f740c444c27e61e025a74ed99955f2ea0288 Mon Sep 17 00:00:00 2001 From: Julien Viard de Galbert Date: Sat, 7 Nov 2020 23:40:43 +0100 Subject: src/soc/intel/denverton_ns: Use improvement in coreboot since 4.9 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - enable microcode in cbfs (won't boot without microcode) - force num fit entry to 1 to avoid crash in cbfstool/fit.c - re-enable FSP-CAR (tested to boot, while I couldn't boot with NEM) - enable io driver for uart in legacy mode (ie emulating legacy port by configuring the pci to legacy io address and hiding the pci device) Signed-off-by: Julien Viard de Galbert Change-Id: Ibc5ce91118c6052af23642fb3461f574cd888dea Reviewed-on: https://review.coreboot.org/c/coreboot/+/47340 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Felix Singer Reviewed-by: Mariusz Szafrański --- src/soc/intel/denverton_ns/Kconfig | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) (limited to 'src/soc') diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 89bbbb0c45..4981205f09 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -7,6 +7,10 @@ config SOC_INTEL_DENVERTON_NS if SOC_INTEL_DENVERTON_NS +config CPU_INTEL_NUM_FIT_ENTRIES + int + default 1 + config CPU_SPECIFIC_OPTIONS def_bool y select ARCH_ALL_STAGES_X86_32 @@ -21,6 +25,7 @@ config CPU_SPECIFIC_OPTIONS select CACHE_MRC_SETTINGS select PARALLEL_MP select PCR_COMMON_IOSF_1_0 + select SUPPORT_CPU_UCODE_IN_CBFS select INTEL_DESCRIPTOR_MODE_CAPABLE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_CPU @@ -134,6 +139,9 @@ config LEGACY_UART_MODE bool "Legacy Mode" help Enable legacy UART mode + select CONSOLE_SERIAL + select DRIVERS_UART + select DRIVERS_UART_8250IO endchoice config ENABLE_HSUART @@ -153,10 +161,14 @@ config C_ENV_BOOTBLOCK_SIZE hex default 0x8000 -config DENVERTON_NS_CAR_NEM_ENHANCED +choice + prompt "Cache-as-ram implementation" + default USE_DENVERTON_NS_CAR_NEM_ENHANCED + help + This option allows you to select how cache-as-ram (CAR) is set up. + +config USE_DENVERTON_NS_CAR_NEM_ENHANCED bool "Enhanced Non-evict mode" - depends on !FSP_CAR - default y select SOC_INTEL_COMMON_BLOCK_CAR select USE_CAR_NEM_ENHANCED_V1 help @@ -167,4 +179,12 @@ config DENVERTON_NS_CAR_NEM_ENHANCED ENHANCED NEM guarantees that modified data is always kept in cache while clean data is replaced. +config USE_DENVERTON_NS_FSP_CAR + bool "Use FSP CAR" + select FSP_CAR + help + Use FSP APIs to initialize and tear down the Cache-As-Ram. + +endchoice + endif ## SOC_INTEL_DENVERTON_NS -- cgit v1.2.3