From 183092743b85533bdbd2e5a706980561786dbd34 Mon Sep 17 00:00:00 2001 From: Krishna Prasad Bhat Date: Thu, 21 Sep 2023 23:54:53 +0530 Subject: soc/intel/mtl: Override SOC_INTEL_CSE_FW_PARTITION_CMOS_OFFSET CSE firmware downgrade and PSR data backup flows involve global resets, there is a need to track the PSR data backup status across resets. In the subsequent patches, a CMOS structure to store PSR back-up status will be added. The current SOC_INTEL_CSE_FW_PARTITION_CMOS_OFFSET of 68 can only store cse_specific_info, as ramtop is at offset 100 and PSR back-up status structure will not be able to fit within the range. This patch overrides the SOC_INTEL_CSE_FW_PARTITION_CMOS_OFFSET to 161 to accommodate all CSE related info in adjacent CMOS memory. BUG=b:273207144 TEST=Verify CSE RW FW versions are stored in CMOS memory in rex. Change-Id: I8bae5245f93b99be15b4e59cfeffbc23eec95001 Signed-off-by: Krishna Prasad Bhat Signed-off-by: Rizwan Qureshi Reviewed-on: https://review.coreboot.org/c/coreboot/+/78054 Reviewed-by: Kapil Porwal Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/soc/intel/meteorlake/Kconfig | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'src/soc') diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 1c61547fb6..a416e88c75 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -439,4 +439,14 @@ config IOE_DIE_CLOCK_START config HAVE_BMP_LOGO_COMPRESS_LZMA default n +# The default offset to store CSE RW FW version information is at 68. +# However, in Intel Meteor Lake based systems that use PSR, the additional +# size required to keep CSE RW FW version information and PSR back-up status +# in adjacent CMOS memory at offset 68 is not available. Therefore, we +# override the default offset to 161, which has enough space to keep both +# the CSE related information together. +config SOC_INTEL_CSE_FW_PARTITION_CMOS_OFFSET + int + default 161 + endif -- cgit v1.2.3