From 15ccbf042ddda877cde23e9b0d5d3f5256e62c33 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 20 Mar 2019 15:09:44 +0530 Subject: {northbridge, soc, southbridge}/intel: Make use of generic set_subsystem() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch removes all local definitions of sub_system functions and make use of common generic pci_dev_set_subsystem() from PCI bridge and Cardbus devices as well. Change-Id: I5fbed39ed448baf11f0e0786ce0ee94741d57237 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/31950 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Furquan Shaikh --- src/soc/intel/broadwell/pcie.c | 12 +----------- src/soc/intel/common/block/pcie/pcie.c | 11 +---------- 2 files changed, 2 insertions(+), 21 deletions(-) (limited to 'src/soc') diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index 32135eedbb..472e8da465 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -649,16 +649,6 @@ static void pch_pcie_enable(struct device *dev) root_port_commit_config(); } -static void pcie_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - /* NOTE: This is not the default position! */ - if (!vendor || !device) - pci_write_config32(dev, 0x94, pci_read_config32(dev, 0)); - else - pci_write_config32(dev, 0x94, (device << 16) | vendor); -} - static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int off) { /* Set max snoop and non-snoop latency for Broadwell */ @@ -666,7 +656,7 @@ static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int off) } static struct pci_operations pcie_ops = { - .set_subsystem = pcie_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, .set_L1_ss_latency = pcie_set_L1_ss_max_latency, }; diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index 82957657f5..d74b09826c 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -25,8 +25,6 @@ #define PCIE_LTR_MAX_NO_SNOOP_LATENCY_VALUE 0x1003 /* Latency tolerance reporting, max snoop latency value 3.14ms */ #define PCIE_LTR_MAX_SNOOP_LATENCY_VALUE 0x1003 -/* PCI-E Sub-System ID */ -#define PCIE_SUBSYSTEM_VENDOR_ID 0x94 static void pch_pcie_init(struct device *dev) { @@ -72,16 +70,9 @@ static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int offset) PCIE_LTR_MAX_SNOOP_LATENCY_VALUE); } -static void pcie_dev_set_subsystem(struct device *dev, - unsigned int vendor, unsigned int device) -{ - pci_write_config32(dev, PCIE_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - static struct pci_operations pcie_ops = { .set_L1_ss_latency = pcie_set_L1_ss_max_latency, - .set_subsystem = pcie_dev_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations device_ops = { -- cgit v1.2.3