From 104308090058914657a032cdcbd3a869846f31b4 Mon Sep 17 00:00:00 2001 From: Shuo Liu Date: Tue, 19 Mar 2024 02:06:30 +0800 Subject: soc/intel/xeon_sp: Use fixed BDF for IBL Integrated Boot Logic (IBL) codes doesn't support bootloader controlled Primary-to-Sideband Bridge (P2SB) hidden and unhidden. Hence, dynamically read IBL HPET/IOAPIC Bus:Device.Function (BDF) by bootloader is not supported, because when P2SB is hidden the register access is denied. TEST=Build and boot on intel/archercity CRB TEST=Build on intel/avenuecity CRB TEST=Build on intel/beechnutcity CRB Change-Id: I3975cb00e215c4984c63bb8510e8aef7d4cc85a4 Signed-off-by: Shuo Liu Reviewed-on: https://review.coreboot.org/c/coreboot/+/81321 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/include/soc/util.h | 3 +++ src/soc/intel/xeon_sp/uncore_acpi.c | 5 ++--- src/soc/intel/xeon_sp/util.c | 28 ++++++++++++++++++++++++++++ 3 files changed, 33 insertions(+), 3 deletions(-) (limited to 'src/soc') diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h index 734455a50d..af749023b5 100644 --- a/src/soc/intel/xeon_sp/include/soc/util.h +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -4,6 +4,7 @@ #define _XEON_SP_SOC_UTIL_H_ #include +#include #include #define MEM_ADDR_64MB_SHIFT_BITS 26 @@ -27,6 +28,8 @@ bool is_ubox_stack_res(const xSTACK_RES *res); bool is_ioat_iio_stack_res(const xSTACK_RES *res); bool is_iio_cxl_stack_res(const xSTACK_RES *res); void bios_done_msr(void *unused); +union p2sb_bdf soc_get_hpet_bdf(void); +union p2sb_bdf soc_get_ioapic_bdf(void); enum xeonsp_cxl_mode get_cxl_mode(void); diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c index c9e8ccb7f9..95f1492775 100644 --- a/src/soc/intel/xeon_sp/uncore_acpi.c +++ b/src/soc/intel/xeon_sp/uncore_acpi.c @@ -18,7 +18,6 @@ #include #include #include -#include #include "chip.h" /* NUMA related ACPI table generation. SRAT, SLIT, etc */ @@ -283,7 +282,7 @@ static unsigned long acpi_create_drhd(unsigned long current, struct device *iomm // Add PCH IOAPIC if (is_dev_on_domain0(iommu)) { - union p2sb_bdf ioapic_bdf = p2sb_get_ioapic_bdf(); + union p2sb_bdf ioapic_bdf = soc_get_ioapic_bdf(); printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " "PCI Path: 0x%x, 0x%x\n", get_ioapic_id(IO_APIC_ADDR), ioapic_bdf.bus, ioapic_bdf.dev, ioapic_bdf.fn); @@ -363,7 +362,7 @@ static unsigned long acpi_create_drhd(unsigned long current, struct device *iomm //BIT 15 if (num_hpets && (num_hpets != 0x1f) && (read32p(HPET_BASE_ADDRESS + 0x100) & (0x00008000))) { - union p2sb_bdf hpet_bdf = p2sb_get_hpet_bdf(); + union p2sb_bdf hpet_bdf = soc_get_hpet_bdf(); printk(BIOS_DEBUG, " [Message-capable HPET Device] Enumeration ID: 0x%x, " "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", 0, hpet_bdf.bus, hpet_bdf.dev, hpet_bdf.fn); diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c index 5c63f18a93..2fdf45e04f 100644 --- a/src/soc/intel/xeon_sp/util.c +++ b/src/soc/intel/xeon_sp/util.c @@ -9,8 +9,10 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -88,6 +90,32 @@ unsigned int soc_get_num_cpus(void) return get_iio_uds()->SystemStatus.numCpus; } +union p2sb_bdf soc_get_hpet_bdf(void) +{ + if (CONFIG(SOC_INTEL_COMMON_IBL_BASE)) { + union p2sb_bdf bdf = { + .bus = HPET_BUS_NUM, + .dev = HPET_DEV_NUM, + .fn = HPET0_FUNC_NUM + }; + return bdf; + } + return p2sb_get_hpet_bdf(); +} + +union p2sb_bdf soc_get_ioapic_bdf(void) +{ + if (CONFIG(SOC_INTEL_COMMON_IBL_BASE)) { + union p2sb_bdf bdf = { + .bus = PCH_IOAPIC_BUS_NUMBER, + .dev = PCH_IOAPIC_DEV_NUM, + .fn = PCH_IOAPIC_FUNC_NUM + }; + return bdf; + } + return p2sb_get_ioapic_bdf(); +} + #if ENV_RAMSTAGE /* Setting devtree variables is only allowed in ramstage. */ void lock_pam0123(void) -- cgit v1.2.3