From 0fec867e32a2df821e5a3569496b1dda7a2b1d5f Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 25 May 2021 21:07:23 +0200 Subject: soc/amd/picasso: add devicetree setting for PSPP policy Since the default for the corresponding UPD of the Picasso FSP is DXIO_PSPP_POWERSAVE and the devicetree default is DXIO_PSPP_PERFORMANCE, add a deviectree setting for each board that's using the Picasso SoC code to not change the setting for the existing boards. Signed-off-by: Felix Held Change-Id: I0008ebb0c0f339ed3bdf24ab95a20aa83d5be2c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54934 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/soc/amd/picasso/chip.h | 7 +++++++ src/soc/amd/picasso/fsp_m_params.c | 3 +++ 2 files changed, 10 insertions(+) (limited to 'src/soc') diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 359fa956f8..4c43b1fdff 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -263,6 +263,13 @@ struct soc_amd_picasso_config { GPP_CLK_OFF, /* GPP clk off */ } gpp_clk_config[GPP_CLK_OUTPUT_COUNT]; + /* performance policy for the PCIe links: power consumption vs. link speed */ + enum { + DXIO_PSPP_PERFORMANCE = 0, + DXIO_PSPP_BALANCED, + DXIO_PSPP_POWERSAVE, + } pspp_policy; + /* If using an external 48MHz OSC for codec, will disable internal X48M_OSC */ bool acp_i2s_use_external_48mhz_osc; diff --git a/src/soc/amd/picasso/fsp_m_params.c b/src/soc/amd/picasso/fsp_m_params.c index f196e48f12..3532fb2c2c 100644 --- a/src/soc/amd/picasso/fsp_m_params.c +++ b/src/soc/amd/picasso/fsp_m_params.c @@ -112,5 +112,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) mcfg->sata_enable = devtree_sata_dev_enabled(); mcfg->hdmi2_disable = config->hdmi2_disable; + /* PCIe power vs. speed */ + mcfg->pspp_policy = config->pspp_policy; + mainboard_updm_update(mcfg); } -- cgit v1.2.3