From 0f973d6e61d4bda614ea004939f324da3d61347b Mon Sep 17 00:00:00 2001 From: Naresh Solanki Date: Thu, 14 Sep 2023 10:58:07 +0200 Subject: soc/intel/xeon_sp/spr: Add SATA controllers 1 and 2 to devicetree The board has three SATA controllers, so add the remaining two on PCI device 18.0 and 19.0. TEST=Verify in lspci the sata controllers. Change-Id: Ia654c4ef895b52338554d89c25f61b262fbbcbbb Signed-off-by: Naresh Solanki Reviewed-on: https://review.coreboot.org/c/coreboot/+/77892 Reviewed-by: Annie Chen Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Patrick Rudolph --- src/soc/intel/xeon_sp/spr/chipset.cb | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src/soc') diff --git a/src/soc/intel/xeon_sp/spr/chipset.cb b/src/soc/intel/xeon_sp/spr/chipset.cb index 79a85965ff..a674af97d5 100644 --- a/src/soc/intel/xeon_sp/spr/chipset.cb +++ b/src/soc/intel/xeon_sp/spr/chipset.cb @@ -50,7 +50,9 @@ chip soc/intel/xeon_sp/spr device pci 16.4 on end # Intel device 1be4: PCH ME HECI #3 device pci 16.5 on end # Intel device 1be5: PCH ME HECI #4 device pci 16.6 on end # Intel device 1be6 - device pci 17.0 on end # Intel device 1ba2: PCH SATA controller (AHCI) + device pci 17.0 on end # Intel device 1ba2: PCH SATA controller 0 (AHCI) + device pci 18.0 on end # Intel device 1bf2: PCH SATA controller 1 (AHCI) + device pci 19.0 on end # Intel device 1bd2: PCH SATA controller 2 (AHCI) device pci 1a.0 on end # Intel device 1bb4: PCH PCIe Root Port #12 device pci 1b.0 on end # Intel device 1bb5: PCH PCIe Root Port #13 device pci 1e.0 on end # Intel device Communication controller: Intel Corporation Device 1bad -- cgit v1.2.3