From 0b07e36a1fb7e48dc31aa6b630e3f7069a23e259 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Thu, 1 Jun 2023 23:22:11 +0200
Subject: soc/amd/stoneyridge/acpi: rename sb_fch.asl to mmio.asl

This file only contain the ACPI code describing the MMIO devices in the
FCH, so rename it to mmio.asl. This also brings the Stoneyridge ACPI
code a bit more in line with the ACPI code of the other SoCs.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iccef1fc5230e3e104d8dea586a9cbaf894471c12
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75597
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/stoneyridge/acpi/mmio.asl   | 140 ++++++++++++++++++++++++++++++++
 src/soc/amd/stoneyridge/acpi/sb_fch.asl | 140 --------------------------------
 src/soc/amd/stoneyridge/acpi/soc.asl    |   4 +-
 3 files changed, 142 insertions(+), 142 deletions(-)
 create mode 100644 src/soc/amd/stoneyridge/acpi/mmio.asl
 delete mode 100644 src/soc/amd/stoneyridge/acpi/sb_fch.asl

(limited to 'src/soc')

diff --git a/src/soc/amd/stoneyridge/acpi/mmio.asl b/src/soc/amd/stoneyridge/acpi/mmio.asl
new file mode 100644
index 0000000000..ef2b4eab62
--- /dev/null
+++ b/src/soc/amd/stoneyridge/acpi/mmio.asl
@@ -0,0 +1,140 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+#include <soc/iomap.h>
+#include <amdblocks/acpimmio_map.h>
+
+Device (AAHB)
+{
+	Name (_HID, "AAHB0000")
+	Name (_UID, 0x0)
+	Name (_CRS, ResourceTemplate()
+	{
+		Memory32Fixed (ReadWrite, ALINK_AHB_ADDRESS, 0x2000)
+	})
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (0x0b)
+	}
+}
+
+Device (GPIO)
+{
+	Name (_HID, GPIO_DEVICE_NAME)
+	Name (_CID, GPIO_DEVICE_NAME)
+	Name (_UID, 0)
+	Name (_DDN, GPIO_DEVICE_DESC)
+
+	Name (_CRS, ResourceTemplate()
+	{
+		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
+			{ 7 }
+		Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x300)
+	})
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+}
+
+Device (FUR0)
+{
+	Name (_HID, "AMD0020")
+	Name (_UID, 0x0)
+	Name (_CRS, ResourceTemplate()
+	{
+		IRQ (Edge, ActiveHigh, Exclusive) { 10 }
+		Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x2000)
+	})
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+}
+
+Device (FUR1) {
+	Name (_HID, "AMD0020")
+	Name (_UID, 0x1)
+	Name (_CRS, ResourceTemplate()
+	{
+			IRQ (Edge, ActiveHigh, Exclusive) { 11 }
+			Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x2000)
+	})
+	Method (_STA, 0x0, NotSerialized)
+	{
+			Return (0x0F)
+	}
+}
+
+Device (I2CA) {
+	Name (_HID, "AMD0010")
+	Name (_UID, 0x0)
+	Name (_CRS, ResourceTemplate()
+	{
+		IRQ (Edge, ActiveHigh, Exclusive) { 3 }
+		Memory32Fixed (ReadWrite, APU_I2C0_BASE, 0x1000)
+	})
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+}
+
+Device (I2CB)
+{
+	Name (_HID, "AMD0010")
+	Name (_UID, 0x1)
+	Name (_CRS, ResourceTemplate()
+	{
+		IRQ (Edge, ActiveHigh, Exclusive) { 15 }
+		Memory32Fixed (ReadWrite, APU_I2C1_BASE, 0x1000)
+	})
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+}
+
+Device (I2CC) {
+	Name (_HID, "AMD0010")
+	Name (_UID, 0x2)
+	Name (_CRS, ResourceTemplate()
+	{
+		IRQ (Edge, ActiveHigh, Exclusive) { 6 }
+		Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000)
+	})
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+}
+
+Device (I2CD)
+{
+	Name (_HID, "AMD0010")
+	Name (_UID, 0x3)
+	Name (_CRS, ResourceTemplate() {
+		IRQ (Edge, ActiveHigh, Exclusive) { 14 }
+		Memory32Fixed(ReadWrite, APU_I2C3_BASE, 0x1000)
+	})
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+}
+
+Device (MISC)
+{
+	Name (_HID, "AMD0040")
+	Name (_UID, 0x3)
+	Name (_CRS, ResourceTemplate() {
+		Memory32Fixed(ReadWrite, ACPIMMIO_MISC_BASE, 0x100)
+	})
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (0x0b)
+	}
+}
diff --git a/src/soc/amd/stoneyridge/acpi/sb_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_fch.asl
deleted file mode 100644
index ef2b4eab62..0000000000
--- a/src/soc/amd/stoneyridge/acpi/sb_fch.asl
+++ /dev/null
@@ -1,140 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <soc/gpio.h>
-#include <soc/iomap.h>
-#include <amdblocks/acpimmio_map.h>
-
-Device (AAHB)
-{
-	Name (_HID, "AAHB0000")
-	Name (_UID, 0x0)
-	Name (_CRS, ResourceTemplate()
-	{
-		Memory32Fixed (ReadWrite, ALINK_AHB_ADDRESS, 0x2000)
-	})
-	Method (_STA, 0x0, NotSerialized)
-	{
-		Return (0x0b)
-	}
-}
-
-Device (GPIO)
-{
-	Name (_HID, GPIO_DEVICE_NAME)
-	Name (_CID, GPIO_DEVICE_NAME)
-	Name (_UID, 0)
-	Name (_DDN, GPIO_DEVICE_DESC)
-
-	Name (_CRS, ResourceTemplate()
-	{
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
-			{ 7 }
-		Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x300)
-	})
-
-	Method (_STA, 0x0, NotSerialized)
-	{
-		Return (0x0F)
-	}
-}
-
-Device (FUR0)
-{
-	Name (_HID, "AMD0020")
-	Name (_UID, 0x0)
-	Name (_CRS, ResourceTemplate()
-	{
-		IRQ (Edge, ActiveHigh, Exclusive) { 10 }
-		Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x2000)
-	})
-	Method (_STA, 0x0, NotSerialized)
-	{
-		Return (0x0F)
-	}
-}
-
-Device (FUR1) {
-	Name (_HID, "AMD0020")
-	Name (_UID, 0x1)
-	Name (_CRS, ResourceTemplate()
-	{
-			IRQ (Edge, ActiveHigh, Exclusive) { 11 }
-			Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x2000)
-	})
-	Method (_STA, 0x0, NotSerialized)
-	{
-			Return (0x0F)
-	}
-}
-
-Device (I2CA) {
-	Name (_HID, "AMD0010")
-	Name (_UID, 0x0)
-	Name (_CRS, ResourceTemplate()
-	{
-		IRQ (Edge, ActiveHigh, Exclusive) { 3 }
-		Memory32Fixed (ReadWrite, APU_I2C0_BASE, 0x1000)
-	})
-
-	Method (_STA, 0x0, NotSerialized)
-	{
-		Return (0x0F)
-	}
-}
-
-Device (I2CB)
-{
-	Name (_HID, "AMD0010")
-	Name (_UID, 0x1)
-	Name (_CRS, ResourceTemplate()
-	{
-		IRQ (Edge, ActiveHigh, Exclusive) { 15 }
-		Memory32Fixed (ReadWrite, APU_I2C1_BASE, 0x1000)
-	})
-	Method (_STA, 0x0, NotSerialized)
-	{
-		Return (0x0F)
-	}
-}
-
-Device (I2CC) {
-	Name (_HID, "AMD0010")
-	Name (_UID, 0x2)
-	Name (_CRS, ResourceTemplate()
-	{
-		IRQ (Edge, ActiveHigh, Exclusive) { 6 }
-		Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000)
-	})
-
-	Method (_STA, 0x0, NotSerialized)
-	{
-		Return (0x0F)
-	}
-}
-
-Device (I2CD)
-{
-	Name (_HID, "AMD0010")
-	Name (_UID, 0x3)
-	Name (_CRS, ResourceTemplate() {
-		IRQ (Edge, ActiveHigh, Exclusive) { 14 }
-		Memory32Fixed(ReadWrite, APU_I2C3_BASE, 0x1000)
-	})
-	Method (_STA, 0x0, NotSerialized)
-	{
-		Return (0x0F)
-	}
-}
-
-Device (MISC)
-{
-	Name (_HID, "AMD0040")
-	Name (_UID, 0x3)
-	Name (_CRS, ResourceTemplate() {
-		Memory32Fixed(ReadWrite, ACPIMMIO_MISC_BASE, 0x100)
-	})
-	Method (_STA, 0x0, NotSerialized)
-	{
-		Return (0x0b)
-	}
-}
diff --git a/src/soc/amd/stoneyridge/acpi/soc.asl b/src/soc/amd/stoneyridge/acpi/soc.asl
index 47d5992272..6e67f5a3fa 100644
--- a/src/soc/amd/stoneyridge/acpi/soc.asl
+++ b/src/soc/amd/stoneyridge/acpi/soc.asl
@@ -15,8 +15,8 @@ Scope(PCI0) {
 /* Describe PCI INT[A-H] for the Southbridge */
 #include "pci_int.asl"
 
-/* Describe the devices in the Southbridge */
-#include "sb_fch.asl"
+/* Describe the MMIO devices in the FCH */
+#include "mmio.asl"
 
 /* Add GPIO library */
 #include <soc/amd/common/acpi/gpio_bank_lib.asl>
-- 
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