From 0aed4e577df03a3c9c790fddebb1a9c413a0abcb Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 12 Oct 2020 17:27:31 +0530 Subject: soc/intel/alderlake: Enable TME for Alder Lake List of changes: 1. Select CONFIG_INTEL_TME from SoC Kconfig 2. Set TmeEnable FSP-M UPD based on Kconfig. TEST=Able to build and boot ADLRVP and verified from Chrome OS that TME is enable. Change-Id: I6992957bd2999a2efbae7b6d9c825c43bd118f72 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/46296 Reviewed-by: Angel Pons Reviewed-by: V Sowmya Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/intel/alderlake/Kconfig | 1 + src/soc/intel/alderlake/romstage/fsp_params.c | 2 ++ 2 files changed, 3 insertions(+) (limited to 'src/soc') diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 3f500f33cf..2d21a61193 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -25,6 +25,7 @@ config CPU_SPECIFIC_OPTIONS select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC + select INTEL_TME select MRC_SETTINGS_PROTECT select PARALLEL_MP select PARALLEL_MP_AP_WORK diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 80420f0948..38c1a1b279 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -155,6 +155,8 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* Skip CPU side PCIe enablement in FSP if device is disabled in devicetree */ dev = pcidev_path_on_root(SA_DEVFN_CPU_PCIE); m_cfg->CpuPcieRpEnableMask = is_dev_enabled(dev); + + m_cfg->TmeEnable = CONFIG(INTEL_TME); } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -- cgit v1.2.3