From 095f97b58f10087b1350e62d8162827c8689c7a2 Mon Sep 17 00:00:00 2001 From: Bernardo Perez Priego Date: Tue, 18 May 2021 18:39:19 -0700 Subject: soc/intel/alderlake: Add TBT PCIe root ports enablement Ports are enabled according to devicetree. BUG=none TEST=Boot device, TBT should be functional Signed-off-by: Bernardo Perez Priego Change-Id: I57e8eb13484014c17d24ad564643f0d03d11bc58 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54643 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/alderlake/fsp_params.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/soc') diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 78162311d5..0170eecffd 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -251,6 +251,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->ThcPort0Assignment = is_devfn_enabled(PCH_DEVFN_THC0) ? THC_0 : THC_NONE; params->ThcPort1Assignment = is_devfn_enabled(PCH_DEVFN_THC1) ? THC_1 : THC_NONE; + /* USB4/TBT */ + for (i = 0; i < ARRAY_SIZE(params->ITbtPcieRootPortEn); i++) + params->ITbtPcieRootPortEn[i] = is_devfn_enabled(SA_DEVFN_TBT(i)); + /* Legacy 8254 timer support */ params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER); params->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER); -- cgit v1.2.3