From 08aeda6c14886d39e04382c7fe6d24c4b45c3b0a Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 20 Oct 2019 14:27:40 +0200 Subject: soc/intel/common: Make native and FSP-T CAR init mutually exclusive postcar stage does not consume cpulib.c, so don't include it there. Change-Id: Ie723412dcf09151cdbb41e357ad9c2e4f393cb47 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36168 Reviewed-by: Nico Huber Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/cpu/Makefile.inc | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'src/soc') diff --git a/src/soc/intel/common/block/cpu/Makefile.inc b/src/soc/intel/common/block/cpu/Makefile.inc index 323d15739c..deddb67a16 100644 --- a/src/soc/intel/common/block/cpu/Makefile.inc +++ b/src/soc/intel/common/block/cpu/Makefile.inc @@ -1,13 +1,13 @@ +ifeq ($(CONFIG_FSP_CAR),y) +bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU)+= car/cache_as_ram_fsp.S +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += car/exit_car_fsp.S +else bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/cache_as_ram.S bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += ../../../../../cpu/x86/early_reset.S -bootblock-$(CONFIG_FSP_CAR)+= car/cache_as_ram_fsp.S -bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c - -romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c - postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/exit_car.S -postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c -postcar-$(CONFIG_FSP_CAR) += car/exit_car_fsp.S +endif +bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT) += mp_init.c -- cgit v1.2.3