From 05ea79cf53f8c425b688c322f750acdfb428198a Mon Sep 17 00:00:00 2001 From: Pratik Prajapati Date: Thu, 17 Sep 2020 11:49:11 -0700 Subject: soc/intel/tigerlake: Set TME upd param based on config Set TmeEnable FSP-M upd based on config. TEST: TME ENABLE and LOCK bits get set when Tme is enabled. Signed-off-by: Pratik Prajapati Change-Id: Ia804c88057e17844f055fd852fc0b36cfe316432 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45486 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi Reviewed-by: Subrata Banik --- src/soc/intel/tigerlake/romstage/fsp_params.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc') diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 39572997c3..dc9caee9fb 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -211,6 +211,9 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* Skip CPU side PCIe enablement in FSP if device is disabled in devicetree */ dev = pcidev_path_on_root(SA_DEVFN_CPU_PCIE); m_cfg->CpuPcieRpEnableMask = dev && dev->enabled; + + /* Change TmeEnable UPD value according to INTEL_TME Kconfig */ + m_cfg->TmeEnable = CONFIG(INTEL_TME); } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -- cgit v1.2.3