From 047a9e4ddc76c399329de8b048be6cd8a0607a70 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Sat, 3 Aug 2019 21:28:40 +0300 Subject: amd/picasso: Rename ramtop.c to memmap.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use a name consistent with the more recent soc/intel. Change-Id: I491e609bed00dc79c628b321c74ad7f4cc31b5fe Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34878 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/soc/amd/picasso/Makefile.inc | 6 +- src/soc/amd/picasso/memmap.c | 117 +++++++++++++++++++++++++++++++++++++++ src/soc/amd/picasso/ramtop.c | 117 --------------------------------------- 3 files changed, 120 insertions(+), 120 deletions(-) create mode 100644 src/soc/amd/picasso/memmap.c delete mode 100644 src/soc/amd/picasso/ramtop.c (limited to 'src/soc') diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 7f371928c1..67d8904a13 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -44,7 +44,7 @@ romstage-y += monotonic_timer.c romstage-y += pmutil.c romstage-y += reset.c romstage-y += smbus.c -romstage-y += ramtop.c +romstage-y += memmap.c romstage-$(CONFIG_PICASSO_UART) += uart.c romstage-y += tsc_freq.c romstage-y += southbridge.c @@ -62,7 +62,7 @@ verstage-$(CONFIG_SPI_FLASH) += spi.c postcar-y += monotonic_timer.c postcar-$(CONFIG_PICASSO_UART) += uart.c -postcar-y += ramtop.c +postcar-y += memmap.c postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += i2c.c postcar-y += tsc_freq.c @@ -80,7 +80,7 @@ ramstage-y += reset.c ramstage-y += sata.c ramstage-y += sm.c ramstage-y += smbus.c -ramstage-y += ramtop.c +ramstage-y += memmap.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c ramstage-$(CONFIG_PICASSO_UART) += uart.c diff --git a/src/soc/amd/picasso/memmap.c b/src/soc/amd/picasso/memmap.c new file mode 100644 index 0000000000..09af7e4de7 --- /dev/null +++ b/src/soc/amd/picasso/memmap.c @@ -0,0 +1,117 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define __SIMPLE_DEVICE__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void backup_top_of_low_cacheable(uintptr_t ramtop) +{ + biosram_write32(BIOSRAM_CBMEM_TOP, ramtop); +} + +uintptr_t restore_top_of_low_cacheable(void) +{ + return biosram_read32(BIOSRAM_CBMEM_TOP); +} + +#if CONFIG(ACPI_BERT) + #if CONFIG_SMM_TSEG_SIZE == 0x0 + #define BERT_REGION_MAX_SIZE 0x100000 + #else + /* SMM_TSEG_SIZE must stay on a boundary appropriate for its granularity */ + #define BERT_REGION_MAX_SIZE CONFIG_SMM_TSEG_SIZE + #endif +#else + #define BERT_REGION_MAX_SIZE 0 +#endif + +void bert_reserved_region(void **start, size_t *size) +{ + if (CONFIG(ACPI_BERT)) + *start = cbmem_top(); + else + start = NULL; + *size = BERT_REGION_MAX_SIZE; +} + +void *cbmem_top(void) +{ + msr_t tom = rdmsr(TOP_MEM); + + if (!tom.lo) + return 0; + + /* 8MB alignment to keep MTRR usage low */ + return (void *)ALIGN_DOWN(restore_top_of_low_cacheable() + - CONFIG_SMM_TSEG_SIZE + - BERT_REGION_MAX_SIZE, 8*MiB); +} + +static uintptr_t smm_region_start(void) +{ + return (uintptr_t)cbmem_top() + BERT_REGION_MAX_SIZE; +} + +static size_t smm_region_size(void) +{ + return CONFIG_SMM_TSEG_SIZE; +} + +/* + * For data stored in TSEG, ensure TValid is clear so R/W access can reach + * the DRAM when not in SMM. + */ +static void clear_tvalid(void) +{ + msr_t hwcr = rdmsr(HWCR_MSR); + msr_t mask = rdmsr(SMM_MASK_MSR); + int tvalid = !!(mask.lo & SMM_TSEG_VALID); + + if (hwcr.lo & SMM_LOCK) { + if (!tvalid) /* not valid but locked means still accessible */ + return; + + printk(BIOS_ERR, "Error: can't clear TValid, already locked\n"); + return; + } + + mask.lo &= ~SMM_TSEG_VALID; + wrmsr(SMM_MASK_MSR, mask); +} + +void smm_region(uintptr_t *start, size_t *size) +{ + static int once; + + *start = smm_region_start(); + *size = smm_region_size(); + + if (!once) { + clear_tvalid(); + once = 1; + } +} diff --git a/src/soc/amd/picasso/ramtop.c b/src/soc/amd/picasso/ramtop.c deleted file mode 100644 index 09af7e4de7..0000000000 --- a/src/soc/amd/picasso/ramtop.c +++ /dev/null @@ -1,117 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define __SIMPLE_DEVICE__ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -void backup_top_of_low_cacheable(uintptr_t ramtop) -{ - biosram_write32(BIOSRAM_CBMEM_TOP, ramtop); -} - -uintptr_t restore_top_of_low_cacheable(void) -{ - return biosram_read32(BIOSRAM_CBMEM_TOP); -} - -#if CONFIG(ACPI_BERT) - #if CONFIG_SMM_TSEG_SIZE == 0x0 - #define BERT_REGION_MAX_SIZE 0x100000 - #else - /* SMM_TSEG_SIZE must stay on a boundary appropriate for its granularity */ - #define BERT_REGION_MAX_SIZE CONFIG_SMM_TSEG_SIZE - #endif -#else - #define BERT_REGION_MAX_SIZE 0 -#endif - -void bert_reserved_region(void **start, size_t *size) -{ - if (CONFIG(ACPI_BERT)) - *start = cbmem_top(); - else - start = NULL; - *size = BERT_REGION_MAX_SIZE; -} - -void *cbmem_top(void) -{ - msr_t tom = rdmsr(TOP_MEM); - - if (!tom.lo) - return 0; - - /* 8MB alignment to keep MTRR usage low */ - return (void *)ALIGN_DOWN(restore_top_of_low_cacheable() - - CONFIG_SMM_TSEG_SIZE - - BERT_REGION_MAX_SIZE, 8*MiB); -} - -static uintptr_t smm_region_start(void) -{ - return (uintptr_t)cbmem_top() + BERT_REGION_MAX_SIZE; -} - -static size_t smm_region_size(void) -{ - return CONFIG_SMM_TSEG_SIZE; -} - -/* - * For data stored in TSEG, ensure TValid is clear so R/W access can reach - * the DRAM when not in SMM. - */ -static void clear_tvalid(void) -{ - msr_t hwcr = rdmsr(HWCR_MSR); - msr_t mask = rdmsr(SMM_MASK_MSR); - int tvalid = !!(mask.lo & SMM_TSEG_VALID); - - if (hwcr.lo & SMM_LOCK) { - if (!tvalid) /* not valid but locked means still accessible */ - return; - - printk(BIOS_ERR, "Error: can't clear TValid, already locked\n"); - return; - } - - mask.lo &= ~SMM_TSEG_VALID; - wrmsr(SMM_MASK_MSR, mask); -} - -void smm_region(uintptr_t *start, size_t *size) -{ - static int once; - - *start = smm_region_start(); - *size = smm_region_size(); - - if (!once) { - clear_tvalid(); - once = 1; - } -} -- cgit v1.2.3