From 037ee4b5562099771795d52cf7149ddff8dd3595 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Wed, 8 Jul 2020 16:19:37 -0600 Subject: soc/amd/picasso: Add dummy spinlock for psp_verstage If CONFIG_CMOS_POST is enabled, psp_verstage breaks because the spinlock code is missing. Add dummy spinlock code as the spinlocks aren't needed in the PSP. TEST=Build with CONFIG_CMOS_POST enabled. BUG=None Signed-off-by: Martin Roth Change-Id: Iea6f31e500e1b26f0b974c6eaa486209b9c81459 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43310 Reviewed-by: Raul Rangel Reviewed-by: Karthik Ramasubramanian Reviewed-by: Marshall Dawson Tested-by: build bot (Jenkins) --- .../picasso/psp_verstage/include/arch/smp/spinlock.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 src/soc/amd/picasso/psp_verstage/include/arch/smp/spinlock.h (limited to 'src/soc') diff --git a/src/soc/amd/picasso/psp_verstage/include/arch/smp/spinlock.h b/src/soc/amd/picasso/psp_verstage/include/arch/smp/spinlock.h new file mode 100644 index 0000000000..5245bd1a02 --- /dev/null +++ b/src/soc/amd/picasso/psp_verstage/include/arch/smp/spinlock.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _ARCH_SMP_SPINLOCK_H +#define _ARCH_SMP_SPINLOCK_H + +#define DECLARE_SPIN_LOCK(x) +#define barrier() do {} while (0) +#define spin_is_locked(lock) 0 +#define spin_unlock_wait(lock) do {} while (0) +#define spin_lock(lock) do {} while (0) +#define spin_unlock(lock) do {} while (0) +#define cpu_relax() do {} while (0) + +#include +#define boot_cpu() 1 + +#endif -- cgit v1.2.3