From 027f86e6af023b338a0f1d8a999a8f33eeacb010 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 2 Dec 2022 15:30:10 +0200 Subject: ACPI: Add usb_charge_mode_from_gnvs() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Early Chromebook generations stored the information about USB port power control for S3/S5 sleepstates in GNVS, although the configuration is static. Reduce code duplication and react to ACPI S4 as if it was ACPI S5 request. Change-Id: I7e6f37a023b0e9317dcf0355dfa70e28d51cdad9 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/74524 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier --- src/soc/intel/broadwell/include/soc/nvs.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src/soc') diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h index f627c8076d..52fb711c25 100644 --- a/src/soc/intel/broadwell/include/soc/nvs.h +++ b/src/soc/intel/broadwell/include/soc/nvs.h @@ -30,7 +30,9 @@ struct __packed global_nvs { u8 s33g; /* 0x15 - Enable 3G in S3 */ u8 lids; /* 0x16 - LID State */ u8 unused_was_pwrs; /* 0x17 - AC Power State */ - u32 obsolete_cmem; /* 0x18 - 0x1b - CBMEM TOC */ + u8 s5u1; /* 0x18 - compatibility only */ + u8 s3u1; /* 0x19 - compatibility only */ + u16 unused_incomplete_cmem; /* 0x1a - 0x1b - CBMEM TOC */ u32 unused_was_cbmc; /* 0x1c - 0x1f - coreboot Memory Console */ u64 pm1i; /* 0x20 - 0x27 - PM1 wake status bit */ u64 gpei; /* 0x28 - 0x2f - GPE wake status bit */ -- cgit v1.2.3