From 0201d989f20b3157d52fb9dca01256ebe6550126 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 18 Feb 2024 11:45:30 +0100 Subject: drivers/intel/fsp: Work around multi-socket Xeon-SP pipe init bug Starting with Intel CPX there is a bug in the reference code during the Pipe init. This code synchronises the CAR between sockets in FSP-M. This code implicitly assumes that the FSP heap is right above the RC heap, where both of them are located at the bottom part of CAR. Work around this issue by making that implicit assumption done in FSP explicit in the coreboot linker script and allocation. TEST=intel/archercity CRB Signed-off-by: Arthur Heymans Signed-off-by: Shuo Liu Change-Id: I38a4f4b7470556e528a1672044c31f8bd92887d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80579 Reviewed-by: Lean Sheng Tan Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Shuo Liu --- src/soc/intel/xeon_sp/cpx/Kconfig | 1 + src/soc/intel/xeon_sp/spr/Kconfig | 1 + 2 files changed, 2 insertions(+) (limited to 'src/soc') diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index ac166c3038..b9d63d3ad2 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -7,6 +7,7 @@ config SOC_INTEL_COOPERLAKE_SP select CACHE_MRC_SETTINGS select NO_FSP_TEMP_RAM_EXIT select HAVE_INTEL_FSP_REPO + select FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND help Intel Cooper Lake-SP support diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig index bb88becaa7..ace5c07042 100644 --- a/src/soc/intel/xeon_sp/spr/Kconfig +++ b/src/soc/intel/xeon_sp/spr/Kconfig @@ -13,6 +13,7 @@ config SOC_INTEL_SAPPHIRERAPIDS_SP select SOC_INTEL_CSE_SERVER_SKU select XEON_SP_COMMON_BASE select HAVE_IOAT_DOMAINS + select FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND help Intel Sapphire Rapids-SP support -- cgit v1.2.3