From 5fed693a52ed9746900ce58ec12a2b245f08202e Mon Sep 17 00:00:00 2001
From: Xiang Wang <wxjstz@126.com>
Date: Thu, 12 Jul 2018 14:56:05 +0800
Subject: riscv: add support for modifying compiler options
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Each HART of a SoC like fu540 supports a different ISA. In order for the
coreboot's code can run on each core, need to modify the compile options.
So add this code.

Change-Id: Ie33edc175e612846d4a74f3cbf7520d4145cb68b
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/27442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Philipp Hug <philipp@hug.cx>
---
 src/soc/ucb/riscv/Kconfig | 12 ++++++++++++
 1 file changed, 12 insertions(+)

(limited to 'src/soc/ucb/riscv')

diff --git a/src/soc/ucb/riscv/Kconfig b/src/soc/ucb/riscv/Kconfig
index ff50f6f835..2a73f5c284 100644
--- a/src/soc/ucb/riscv/Kconfig
+++ b/src/soc/ucb/riscv/Kconfig
@@ -10,4 +10,16 @@ config SOC_UCB_RISCV
 
 if SOC_UCB_RISCV
 
+config RISCV_ARCH
+	string
+	default "rv64imafd"
+
+config RISCV_ABI
+	string
+	default "lp64d"
+
+config RISCV_CODEMODEL
+	string
+	default "medany"
+
 endif
-- 
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