From 8c509f36451162dd9a30aa6cc94e8f33e9b50df7 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 29 Nov 2022 19:09:58 +0100 Subject: soc/ti/am335x: Change and optimize memlayout Clang builds (bootblock: 20800 bytes) are slightly larger than GCC builds (bootblock: 18688 bytes) so increase the size of both bootblock and romstage. The technical reference manual mentions no upper limit to the size of the bootblock in the TI header so increasing the bootblock size is allowed. To be able to link the clang bootblock increase it from 20K to 22K. Change-Id: I8719bc3728d4cc8dba8d939cc154c3fc0884d47b Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/70160 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/ti/am335x/memlayout.ld | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'src/soc/ti/am335x') diff --git a/src/soc/ti/am335x/memlayout.ld b/src/soc/ti/am335x/memlayout.ld index 8d1e8d68a6..b9d01a86d6 100644 --- a/src/soc/ti/am335x/memlayout.ld +++ b/src/soc/ti/am335x/memlayout.ld @@ -7,15 +7,15 @@ SECTIONS { SRAM_START(0x402f0400) - BOOTBLOCK(0x402f0400, 20K) - FMAP_CACHE(0x402f0400+20K, 2K) - CBFS_MCACHE(0x402f0400+20K+2K, 8K) - TTB(0x402F8000, 16K) - ROMSTAGE(0x402F8000+16K, 40K) - - PRERAM_CBFS_CACHE(0x402F8000+16K+40K, 20K) - - STACK(0x4030be00, 4K) + BOOTBLOCK(., 22K) + FMAP_CACHE(., 2K) + CBFS_MCACHE(., 8K) + ROMSTAGE(., 42K) + PRERAM_CBFS_CACHE(., 20K) + + STACK(., 4K) + . = ALIGN(16K); + TTB(., 16K) SRAM_END(0x40310000) DRAM_START(0x80000000) -- cgit v1.2.3