From 11cac784ff788b4f0495758d7f5992e457ea552c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 7 Apr 2022 07:16:48 +0300 Subject: Replace some ENV_ROMSTAGE with ENV_RAMINIT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit With a combined bootblock+romstage ENV_ROMSTAGE might no longer evaluate true. Change-Id: I733cf4e4ab177e35cd260318556ece1e73d082dc Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/63376 Reviewed-by: Julius Werner Tested-by: build bot (Jenkins) Reviewed-by: Elyes Haouas Reviewed-by: Raul Rangel --- src/soc/sifive/fu540/clock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/soc/sifive') diff --git a/src/soc/sifive/fu540/clock.c b/src/soc/sifive/fu540/clock.c index 977f938eb4..a8baddef9a 100644 --- a/src/soc/sifive/fu540/clock.c +++ b/src/soc/sifive/fu540/clock.c @@ -56,7 +56,7 @@ static struct prci_ctlr *prci = (void *)FU540_PRCI; #define PRCI_DEVICESRESET_GEMGXL_RST_N(x) (((x) & 0x1) << 5) /* Clock initialization should only be done in romstage. */ -#if ENV_ROMSTAGE +#if ENV_RAMINIT struct pll_settings { unsigned int divr:6; unsigned int divf:9; @@ -247,7 +247,7 @@ void clock_init(void) asm volatile ("fence"); } -#endif /* ENV_ROMSTAGE */ +#endif /* ENV_RAMINIT */ /* Get the core clock's frequency, in KHz */ int clock_get_coreclk_khz(void) -- cgit v1.2.3