From baf27dbaeb1f6791ebfc416f2175507686bd88ac Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Wed, 2 Oct 2019 17:28:56 -0700 Subject: cbfs: Enable CBFS mcache on most chipsets This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is enabled by default. Some older chipsets with insufficient SRAM/CAR space still have it explicitly disabled. All others get the new section added to their memlayout... 8K seems like a sane default to start with. Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/38424 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/sifive/fu540/memlayout.ld | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src/soc/sifive/fu540') diff --git a/src/soc/sifive/fu540/memlayout.ld b/src/soc/sifive/fu540/memlayout.ld index fd63dc0b45..b365b96563 100644 --- a/src/soc/sifive/fu540/memlayout.ld +++ b/src/soc/sifive/fu540/memlayout.ld @@ -12,8 +12,9 @@ SECTIONS { L2LIM_START(FU540_L2LIM) BOOTBLOCK(FU540_L2LIM, 64K) - CAR_STACK(FU540_L2LIM + 64K, 20K) - PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 84K, 8K) + CAR_STACK(FU540_L2LIM + 64K, 12K) + PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 76K, 8K) + CBFS_MCACHE(FU540_L2LIM + 84K, 8K) FMAP_CACHE(FU540_L2LIM + 92K, 2K) ROMSTAGE(FU540_L2LIM + 128K, 128K) PRERAM_CBFS_CACHE(FU540_L2LIM + 256K, 128K) -- cgit v1.2.3