From a5b265bb0ca85cec02c92046904dc0f44f7d6639 Mon Sep 17 00:00:00 2001 From: Xiang Wang Date: Wed, 29 Aug 2018 14:59:32 +0800 Subject: riscv: separately define stack locations at different stages BOOTBLOCK/ROMSTAGE run in CAR/scratchpad. When RAMSTAGE begins execution will enable cache, then CAR will disappear. So the Stack will be separated. Change-Id: I37a0c1928052cabf61ba5c25b440363b75726782 Signed-off-by: Xiang Wang Reviewed-on: https://review.coreboot.org/28383 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/soc/sifive/fu540/include/soc/memlayout.ld | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src/soc/sifive/fu540/include') diff --git a/src/soc/sifive/fu540/include/soc/memlayout.ld b/src/soc/sifive/fu540/include/soc/memlayout.ld index a03c03d345..b9b9c479d6 100644 --- a/src/soc/sifive/fu540/include/soc/memlayout.ld +++ b/src/soc/sifive/fu540/include/soc/memlayout.ld @@ -25,11 +25,12 @@ SECTIONS { L2LIM_START(FU540_L2LIM) BOOTBLOCK(FU540_L2LIM, 64K) - STACK(FU540_L2LIM + 64K, 4K) - PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 68K, 8K) + CAR_STACK(FU540_L2LIM + 64K, 20K) + PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 84K, 8K) ROMSTAGE(FU540_L2LIM + 128K, 128K) L2LIM_END(FU540_L2LIM + 2M) DRAM_START(FU540_DRAM) RAMSTAGE(FU540_DRAM, 256K) + MEM_STACK(FU540_DRAM + 256K, 20K) } -- cgit v1.2.3