From 7c9540ea1d46a776ec92b58f99074f51b430f9bb Mon Sep 17 00:00:00 2001 From: Xiang Wang Date: Thu, 11 Oct 2018 17:30:37 +0800 Subject: riscv: add support smp_pause / smp_resume MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit See https://doc.coreboot.org/arch/riscv/ we know that we need to execute smp_pause at the start of each stage and smp_resume at the end of each stage. Change-Id: I6f8159637bfb15f54f0abeb335de2ba6e9cf82fb Signed-off-by: Xiang Wang Reviewed-on: https://review.coreboot.org/29023 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer Reviewed-by: Philipp Hug --- src/soc/sifive/fu540/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/sifive/fu540/Makefile.inc') diff --git a/src/soc/sifive/fu540/Makefile.inc b/src/soc/sifive/fu540/Makefile.inc index e2bdd03a00..fef859d9e4 100644 --- a/src/soc/sifive/fu540/Makefile.inc +++ b/src/soc/sifive/fu540/Makefile.inc @@ -19,6 +19,7 @@ bootblock-y += media.c bootblock-y += bootblock.c romstage-y += uart.c +romstage-y += clint.c romstage-y += media.c romstage-y += sdram.c romstage-y += cbmem.c -- cgit v1.2.3