From 2e38dbe5f1a9db76cdf529679faee63fcb6a9c34 Mon Sep 17 00:00:00 2001
From: Xiang Wang <wxjstz@126.com>
Date: Tue, 28 Aug 2018 16:34:29 +0800
Subject: riscv: update mtime initialization
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add a interface, which is implemented by SoC.

Change-Id: I5524732f6eb3841e43afd176644119b03b5e5e27
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/28372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
---
 src/soc/sifive/fu540/Makefile.inc | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/soc/sifive/fu540/Makefile.inc')

diff --git a/src/soc/sifive/fu540/Makefile.inc b/src/soc/sifive/fu540/Makefile.inc
index 9e7f584f78..abd3458b28 100644
--- a/src/soc/sifive/fu540/Makefile.inc
+++ b/src/soc/sifive/fu540/Makefile.inc
@@ -14,6 +14,7 @@
 ifeq ($(CONFIG_SOC_SIFIVE_FU540),y)
 
 bootblock-y += uart.c
+bootblock-y += mtime.c
 bootblock-y += media.c
 bootblock-y += bootblock.c
 
-- 
cgit v1.2.3