From 05358047290b5e60cf3c0dc7e967267a03d5c4ce Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Wed, 19 Dec 2018 17:52:43 -0800 Subject: riscv: create Kconfig architecture features for new parts RISCV parts can be created with any one of four CPU modes enabled, with or without PMP, and with either 32 or 64 bit XLEN. In anticipation of parts to come, create the Kconfig variables for these architecture attributes. Change-Id: I32ee51b2a469c7684a2f1b477bdac040e972e253 Signed-off-by: Ronald G. Minnich Reviewed-on: https://review.coreboot.org/c/30348 Reviewed-by: Patrick Georgi Reviewed-by: Stefan Reinauer Tested-by: build bot (Jenkins) --- src/soc/sifive/fu540/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/soc/sifive/fu540/Kconfig') diff --git a/src/soc/sifive/fu540/Kconfig b/src/soc/sifive/fu540/Kconfig index 25b4b46a5d..7910b37860 100644 --- a/src/soc/sifive/fu540/Kconfig +++ b/src/soc/sifive/fu540/Kconfig @@ -14,6 +14,10 @@ config SOC_SIFIVE_FU540 bool select ARCH_RISCV + select ARCH_RISCV_RV64 + select ARCH_RISCV_S + select ARCH_RISCV_U + select ARCH_RISCV_PMP select ARCH_BOOTBLOCK_RISCV select ARCH_VERSTAGE_RISCV select ARCH_ROMSTAGE_RISCV -- cgit v1.2.3