From a342f3937e7ce159fd170ab8cd26ba799a3bc9e4 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 17 Oct 2018 10:56:26 +0200 Subject: src: Remove unneeded whitespace Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/29161 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/samsung/exynos5420/clock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/samsung/exynos5420') diff --git a/src/soc/samsung/exynos5420/clock.c b/src/soc/samsung/exynos5420/clock.c index 3c4bb04794..04125d9cb1 100644 --- a/src/soc/samsung/exynos5420/clock.c +++ b/src/soc/samsung/exynos5420/clock.c @@ -582,7 +582,7 @@ int clock_epll_set_rate(unsigned long rate) epll_con |= epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT; /* - * Required period ( in cycles) to generate a stable clock output. + * Required period (in cycles) to generate a stable clock output. * The maximum clock time can be up to 3000 * PDIV cycles of PLLs * frequency input (as per spec) */ -- cgit v1.2.3