From 74add8b70f39801ff522fdc8c34d983e51a5a634 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Thu, 15 Dec 2016 15:51:13 +0100 Subject: samsung/exynos5420: Fix test for src < 0 It was unsigned, not a good place to be for testing < 0. Change-Id: I126fe86422900bbae2c3ca16052be27985cfed53 Signed-off-by: Patrick Georgi Found-by: Coverity Scan #1241911 Reviewed-on: https://review.coreboot.org/17888 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/soc/samsung/exynos5420/clock.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/soc/samsung/exynos5420') diff --git a/src/soc/samsung/exynos5420/clock.c b/src/soc/samsung/exynos5420/clock.c index 49ac07b115..3c4bb04794 100644 --- a/src/soc/samsung/exynos5420/clock.c +++ b/src/soc/samsung/exynos5420/clock.c @@ -161,7 +161,8 @@ static int clock_select_to_pll(enum peripheral_clock_select sel) unsigned long clock_get_periph_rate(enum periph_id peripheral) { unsigned long sclk; - unsigned int src, div; + unsigned int div; + int src; switch (peripheral) { case PERIPH_ID_UART0: -- cgit v1.2.3