From 46514c2b877c29c2d7c2061a9785736e270c0c62 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 11 Jun 2020 11:59:07 -0700 Subject: treewide: Add Kconfig variable MEMLAYOUT_LD_FILE This change defines a Kconfig variable MEMLAYOUT_LD_FILE which allows SoC/mainboard to provide a linker file for the platform. x86 already provides a default memlayout.ld under src/arch/x86. With this new Kconfig variable, it is possible for the SoC/mainboard code for x86 to provide a custom linker file as well. Makefile.inc is updated for all architectures to use this new Kconfig variable instead of assuming memlayout.ld files under a certain path. All non-x86 boards used memlayout.ld under mainboard directory. However, a lot of these boards were simply including the memlayout from SoC. So, this change also updates these mainboards and SoCs to define the Kconfig as required. BUG=b:155322763 TEST=Verified that abuild with --timeless option results in the same coreboot.rom image for all boards. Change-Id: I6a7f96643ed0519c93967ea2c3bcd881a5d6a4d6 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/42292 Reviewed-by: Paul Menzel Reviewed-by: Raul Rangel Reviewed-by: Julius Werner Tested-by: build bot (Jenkins) --- src/soc/samsung/exynos5420/Kconfig | 4 +++ .../samsung/exynos5420/include/soc/memlayout.ld | 33 ---------------------- src/soc/samsung/exynos5420/memlayout.ld | 33 ++++++++++++++++++++++ 3 files changed, 37 insertions(+), 33 deletions(-) delete mode 100644 src/soc/samsung/exynos5420/include/soc/memlayout.ld create mode 100644 src/soc/samsung/exynos5420/memlayout.ld (limited to 'src/soc/samsung/exynos5420') diff --git a/src/soc/samsung/exynos5420/Kconfig b/src/soc/samsung/exynos5420/Kconfig index 3af8e64ac3..1b80ffca32 100644 --- a/src/soc/samsung/exynos5420/Kconfig +++ b/src/soc/samsung/exynos5420/Kconfig @@ -11,6 +11,10 @@ config CPU_SAMSUNG_EXYNOS5420 if CPU_SAMSUNG_EXYNOS5420 +config MEMLAYOUT_LD_FILE + string + default "src/soc/samsung/exynos5420/memlayout.ld" + config VBOOT select VBOOT_STARTS_IN_ROMSTAGE diff --git a/src/soc/samsung/exynos5420/include/soc/memlayout.ld b/src/soc/samsung/exynos5420/include/soc/memlayout.ld deleted file mode 100644 index e29900110e..0000000000 --- a/src/soc/samsung/exynos5420/include/soc/memlayout.ld +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include - -#include - -/* - * Note: The BootROM loads the 8K BL1 at [0x2020000:0x2022000), so the bootblock - * must be placed after that. After the handoff, the space can be reclaimed. - */ - -SECTIONS -{ - SRAM_START(0x2020000) - /* 17K hole, includes BL1 */ - /* Bootblock is preceded by 16 byte variable length BL2 checksum. */ - BOOTBLOCK(0x2024410, 32K - 16) - /* 15K hole */ - ROMSTAGE(0x2030000, 128K) - /* 32K hole */ - TTB(0x2058000, 16K) - PRERAM_CBFS_CACHE(0x205C000, 74K) - FMAP_CACHE(0x206E800, 2K) - STACK(0x206F000, 16K) - /* 1K hole for weird kernel-shared CPU/SMP state structure that doesn't - * seem to be implemented right now? */ - SRAM_END(0x2074000) - - DRAM_START(0x20000000) - RAMSTAGE(0x20000000, 128K) - POSTRAM_CBFS_CACHE(0x21000000, 8M) - DMA_COHERENT(0x77300000, 1M) -} diff --git a/src/soc/samsung/exynos5420/memlayout.ld b/src/soc/samsung/exynos5420/memlayout.ld new file mode 100644 index 0000000000..e29900110e --- /dev/null +++ b/src/soc/samsung/exynos5420/memlayout.ld @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#include + +/* + * Note: The BootROM loads the 8K BL1 at [0x2020000:0x2022000), so the bootblock + * must be placed after that. After the handoff, the space can be reclaimed. + */ + +SECTIONS +{ + SRAM_START(0x2020000) + /* 17K hole, includes BL1 */ + /* Bootblock is preceded by 16 byte variable length BL2 checksum. */ + BOOTBLOCK(0x2024410, 32K - 16) + /* 15K hole */ + ROMSTAGE(0x2030000, 128K) + /* 32K hole */ + TTB(0x2058000, 16K) + PRERAM_CBFS_CACHE(0x205C000, 74K) + FMAP_CACHE(0x206E800, 2K) + STACK(0x206F000, 16K) + /* 1K hole for weird kernel-shared CPU/SMP state structure that doesn't + * seem to be implemented right now? */ + SRAM_END(0x2074000) + + DRAM_START(0x20000000) + RAMSTAGE(0x20000000, 128K) + POSTRAM_CBFS_CACHE(0x21000000, 8M) + DMA_COHERENT(0x77300000, 1M) +} -- cgit v1.2.3