From 2f37bd65518865688b9234afce0d467508d6f465 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Thu, 19 Feb 2015 14:51:15 -0800 Subject: arm(64): Globally replace writel(v, a) with write32(a, v) This patch is a raw application of the following spatch to src/: @@ expression A, V; @@ - writel(V, A) + write32(A, V) @@ expression A, V; @@ - writew(V, A) + write16(A, V) @@ expression A, V; @@ - writeb(V, A) + write8(A, V) @@ expression A; @@ - readl(A) + read32(A) @@ expression A; @@ - readb(A) + read8(A) BRANCH=none BUG=chromium:444723 TEST=None (depends on next patch) Change-Id: I5dd96490c85ee2bcbc669f08bc6fff0ecc0f9e27 Signed-off-by: Patrick Georgi Original-Commit-Id: 64f643da95d85954c4d4ea91c34a5c69b9b08eb6 Original-Change-Id: I366a2eb5b3a0df2279ebcce572fe814894791c42 Original-Signed-off-by: Julius Werner Original-Reviewed-on: https://chromium-review.googlesource.com/254864 Reviewed-on: http://review.coreboot.org/9836 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/samsung/exynos5420/clock.c | 92 ++++++------- src/soc/samsung/exynos5420/clock_init.c | 200 ++++++++++++++--------------- src/soc/samsung/exynos5420/dmc_common.c | 42 +++--- src/soc/samsung/exynos5420/dmc_init_ddr3.c | 200 ++++++++++++++--------------- src/soc/samsung/exynos5420/dp_lowlevel.c | 2 +- src/soc/samsung/exynos5420/fimd.c | 4 +- src/soc/samsung/exynos5420/gpio.c | 28 ++-- src/soc/samsung/exynos5420/i2c.c | 72 +++++------ src/soc/samsung/exynos5420/power.c | 2 +- src/soc/samsung/exynos5420/smp.c | 22 ++-- src/soc/samsung/exynos5420/spi.c | 18 +-- src/soc/samsung/exynos5420/timer.c | 7 +- src/soc/samsung/exynos5420/tmu.c | 20 +-- src/soc/samsung/exynos5420/trustzone.c | 10 +- src/soc/samsung/exynos5420/uart.c | 20 +-- src/soc/samsung/exynos5420/usb.c | 69 +++------- 16 files changed, 384 insertions(+), 424 deletions(-) (limited to 'src/soc/samsung/exynos5420') diff --git a/src/soc/samsung/exynos5420/clock.c b/src/soc/samsung/exynos5420/clock.c index f6c7845c54..971364ddfe 100644 --- a/src/soc/samsung/exynos5420/clock.c +++ b/src/soc/samsung/exynos5420/clock.c @@ -47,34 +47,34 @@ unsigned long get_pll_clk(int pllreg) switch (pllreg) { case APLL: - r = readl(&exynos_clock->apll_con0); + r = read32(&exynos_clock->apll_con0); break; case MPLL: - r = readl(&exynos_clock->mpll_con0); + r = read32(&exynos_clock->mpll_con0); break; case EPLL: - r = readl(&exynos_clock->epll_con0); - k = readl(&exynos_clock->epll_con1); + r = read32(&exynos_clock->epll_con0); + k = read32(&exynos_clock->epll_con1); break; case VPLL: - r = readl(&exynos_clock->vpll_con0); - k = readl(&exynos_clock->vpll_con1); + r = read32(&exynos_clock->vpll_con0); + k = read32(&exynos_clock->vpll_con1); break; case BPLL: - r = readl(&exynos_clock->bpll_con0); + r = read32(&exynos_clock->bpll_con0); break; case RPLL: - r = readl(&exynos_clock->rpll_con0); - k = readl(&exynos_clock->rpll_con1); + r = read32(&exynos_clock->rpll_con0); + k = read32(&exynos_clock->rpll_con1); break; case SPLL: - r = readl(&exynos_clock->spll_con0); + r = read32(&exynos_clock->spll_con0); break; case CPLL: - r = readl(&exynos_clock->cpll_con0); + r = read32(&exynos_clock->cpll_con0); break; case DPLL: - r = readl(&exynos_clock->dpll_con0); + r = read32(&exynos_clock->dpll_con0); break; default: printk(BIOS_DEBUG, "Unsupported PLL (%d)\n", pllreg); @@ -169,48 +169,48 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral) switch (peripheral) { case PERIPH_ID_UART0: - src = (readl(&exynos_clock->clk_src_peric0) >> 4) & 0x7; - div = (readl(&exynos_clock->clk_div_peric0) >> 8) & 0xf; + src = (read32(&exynos_clock->clk_src_peric0) >> 4) & 0x7; + div = (read32(&exynos_clock->clk_div_peric0) >> 8) & 0xf; break; case PERIPH_ID_UART1: - src = (readl(&exynos_clock->clk_src_peric0) >> 8) & 0x7; - div = (readl(&exynos_clock->clk_div_peric0) >> 12) & 0xf; + src = (read32(&exynos_clock->clk_src_peric0) >> 8) & 0x7; + div = (read32(&exynos_clock->clk_div_peric0) >> 12) & 0xf; break; case PERIPH_ID_UART2: - src = (readl(&exynos_clock->clk_src_peric0) >> 12) & 0x7; - div = (readl(&exynos_clock->clk_div_peric0) >> 16) & 0xf; + src = (read32(&exynos_clock->clk_src_peric0) >> 12) & 0x7; + div = (read32(&exynos_clock->clk_div_peric0) >> 16) & 0xf; break; case PERIPH_ID_UART3: - src = (readl(&exynos_clock->clk_src_peric0) >> 16) & 0x7; - div = (readl(&exynos_clock->clk_div_peric0) >> 20) & 0xf; + src = (read32(&exynos_clock->clk_src_peric0) >> 16) & 0x7; + div = (read32(&exynos_clock->clk_div_peric0) >> 20) & 0xf; break; case PERIPH_ID_PWM0: case PERIPH_ID_PWM1: case PERIPH_ID_PWM2: case PERIPH_ID_PWM3: case PERIPH_ID_PWM4: - src = (readl(&exynos_clock->clk_src_peric0) >> 24) & 0x7; - div = (readl(&exynos_clock->clk_div_peric0) >> 28) & 0x7; + src = (read32(&exynos_clock->clk_src_peric0) >> 24) & 0x7; + div = (read32(&exynos_clock->clk_div_peric0) >> 28) & 0x7; break; case PERIPH_ID_SPI0: - src = (readl(&exynos_clock->clk_src_peric1) >> 20) & 0x7; - div = (readl(&exynos_clock->clk_div_peric1) >> 20) & 0xf; + src = (read32(&exynos_clock->clk_src_peric1) >> 20) & 0x7; + div = (read32(&exynos_clock->clk_div_peric1) >> 20) & 0xf; break; case PERIPH_ID_SPI1: - src = (readl(&exynos_clock->clk_src_peric1) >> 24) & 0x7; - div = (readl(&exynos_clock->clk_div_peric1) >> 24) & 0xf; + src = (read32(&exynos_clock->clk_src_peric1) >> 24) & 0x7; + div = (read32(&exynos_clock->clk_div_peric1) >> 24) & 0xf; break; case PERIPH_ID_SPI2: - src = (readl(&exynos_clock->clk_src_peric1) >> 28) & 0x7; - div = (readl(&exynos_clock->clk_div_peric1) >> 28) & 0xf; + src = (read32(&exynos_clock->clk_src_peric1) >> 28) & 0x7; + div = (read32(&exynos_clock->clk_div_peric1) >> 28) & 0xf; break; case PERIPH_ID_SPI3: /* aka SPI0_ISP */ - src = (readl(&exynos_clock->clk_src_isp) >> 16) & 0x7; - div = (readl(&exynos_clock->clk_div_isp0) >> 0) & 0x7; + src = (read32(&exynos_clock->clk_src_isp) >> 16) & 0x7; + div = (read32(&exynos_clock->clk_div_isp0) >> 0) & 0x7; break; case PERIPH_ID_SPI4: /* aka SPI1_ISP */ - src = (readl(&exynos_clock->clk_src_isp) >> 12) & 0x7; - div = (readl(&exynos_clock->clk_div_isp1) >> 4) & 0x7; + src = (read32(&exynos_clock->clk_src_isp) >> 12) & 0x7; + div = (read32(&exynos_clock->clk_div_isp1) >> 4) & 0x7; break; case PERIPH_ID_I2C0: case PERIPH_ID_I2C1: @@ -229,7 +229,7 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral) * TODO: Add a helper function like with the peripheral clock * select fields? */ - src = (readl(&exynos_clock->clk_src_top1) >> 8) & 0x3; + src = (read32(&exynos_clock->clk_src_top1) >> 8) & 0x3; if (src == 0x0) src = CPLL; else if (src == 0x1) @@ -240,7 +240,7 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral) return -1; sclk = get_pll_clk(src); - div = ((readl(&exynos_clock->clk_div_top1) >> 8) & 0x3f) + 1; + div = ((read32(&exynos_clock->clk_div_top1) >> 8) & 0x3f) + 1; return sclk / div; default: printk(BIOS_DEBUG, "%s: invalid peripheral %d", @@ -267,7 +267,7 @@ unsigned long get_arm_clk(void) unsigned int arm_ratio; unsigned int arm2_ratio; - div = readl(&exynos_clock->clk_div_cpu0); + div = read32(&exynos_clock->clk_div_cpu0); /* ARM_RATIO: [2:0], ARM2_RATIO: [30:28] */ arm_ratio = (div >> 0) & 0x7; @@ -286,7 +286,7 @@ static unsigned long get_mmc_clk(int dev_index) unsigned int sel, ratio; int shift = 0; - sel = readl(&exynos_clock->clk_src_fsys); + sel = read32(&exynos_clock->clk_src_fsys); sel = (sel >> ((dev_index * 4) + 8)) & 0x7; if (sel == 0x3) @@ -296,7 +296,7 @@ static unsigned long get_mmc_clk(int dev_index) else return 0; - ratio = readl(&exynos_clock->clk_div_fsys1); + ratio = read32(&exynos_clock->clk_div_fsys1); shift = dev_index * 10; @@ -316,10 +316,10 @@ void set_mmc_clk(int dev_index, unsigned int div) addr = &exynos_clock->clk_div_fsys1; shift = dev_index * 10; - val = readl(addr); + val = read32(addr); val &= ~(0x3ff << shift); val |= (div & 0x3ff) << shift; - writel(val, addr); + write32(addr, val); } /* Set DW MMC Controller clock */ @@ -546,10 +546,10 @@ int clock_set_mshci(enum periph_id peripheral) printk(BIOS_DEBUG, "invalid peripheral\n"); return -1; } - tmp = readl(addr) & ~0xff0f; + tmp = read32(addr) & ~0xff0f; for (i = 0; i <= 0xf; i++) { if ((clock / (i + 1)) <= 400) { - writel(tmp | i << 0, addr); + write32(addr, tmp | i << 0); break; } } @@ -563,7 +563,7 @@ int clock_epll_set_rate(unsigned long rate) unsigned int lockcnt; struct stopwatch sw; - epll_con = readl(&exynos_clock->epll_con0); + epll_con = read32(&exynos_clock->epll_con0); epll_con &= ~((EPLL_CON0_LOCK_DET_EN_MASK << EPLL_CON0_LOCK_DET_EN_SHIFT) | EPLL_CON0_MDIV_MASK << EPLL_CON0_MDIV_SHIFT | @@ -591,13 +591,13 @@ int clock_epll_set_rate(unsigned long rate) */ lockcnt = 3000 * epll_div[i].p_div; - writel(lockcnt, &exynos_clock->epll_lock); - writel(epll_con, &exynos_clock->epll_con0); - writel(epll_con_k, &exynos_clock->epll_con1); + write32(&exynos_clock->epll_lock, lockcnt); + write32(&exynos_clock->epll_con0, epll_con); + write32(&exynos_clock->epll_con1, epll_con_k); stopwatch_init_msecs_expire(&sw, TIMEOUT_EPLL_LOCK); - while (!(readl(&exynos_clock->epll_con0) & + while (!(read32(&exynos_clock->epll_con0) & (0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT))) { if (stopwatch_expired(&sw)) { printk(BIOS_DEBUG, "%s: Timeout waiting for EPLL lock\n", __func__); diff --git a/src/soc/samsung/exynos5420/clock_init.c b/src/soc/samsung/exynos5420/clock_init.c index 25b8beecd1..c5b4aaaa3f 100644 --- a/src/soc/samsung/exynos5420/clock_init.c +++ b/src/soc/samsung/exynos5420/clock_init.c @@ -35,186 +35,186 @@ void system_clock_init(void) exynos_mct->g_tcon |= (1 << 8); /* PLL locktime */ - writel(APLL_LOCK_VAL, &exynos_clock->apll_lock); - writel(MPLL_LOCK_VAL, &exynos_clock->mpll_lock); - writel(BPLL_LOCK_VAL, &exynos_clock->bpll_lock); - writel(CPLL_LOCK_VAL, &exynos_clock->cpll_lock); - writel(DPLL_LOCK_VAL, &exynos_clock->dpll_lock); - writel(EPLL_LOCK_VAL, &exynos_clock->epll_lock); - writel(VPLL_LOCK_VAL, &exynos_clock->vpll_lock); - writel(IPLL_LOCK_VAL, &exynos_clock->ipll_lock); - writel(SPLL_LOCK_VAL, &exynos_clock->spll_lock); - writel(KPLL_LOCK_VAL, &exynos_clock->kpll_lock); - writel(RPLL_LOCK_VAL, &exynos_clock->rpll_lock); + write32(&exynos_clock->apll_lock, APLL_LOCK_VAL); + write32(&exynos_clock->mpll_lock, MPLL_LOCK_VAL); + write32(&exynos_clock->bpll_lock, BPLL_LOCK_VAL); + write32(&exynos_clock->cpll_lock, CPLL_LOCK_VAL); + write32(&exynos_clock->dpll_lock, DPLL_LOCK_VAL); + write32(&exynos_clock->epll_lock, EPLL_LOCK_VAL); + write32(&exynos_clock->vpll_lock, VPLL_LOCK_VAL); + write32(&exynos_clock->ipll_lock, IPLL_LOCK_VAL); + write32(&exynos_clock->spll_lock, SPLL_LOCK_VAL); + write32(&exynos_clock->kpll_lock, KPLL_LOCK_VAL); + write32(&exynos_clock->rpll_lock, RPLL_LOCK_VAL); setbits_le32(&exynos_clock->clk_src_cpu, MUX_HPM_SEL_MASK); - writel(0, &exynos_clock->clk_src_top6); + write32(&exynos_clock->clk_src_top6, 0); - writel(0, &exynos_clock->clk_src_cdrex); - writel(SRC_KFC_HPM_SEL, &exynos_clock->clk_src_kfc); - writel(HPM_RATIO, &exynos_clock->clk_div_cpu1); - writel(CLK_DIV_CPU0_VAL, &exynos_clock->clk_div_cpu0); + write32(&exynos_clock->clk_src_cdrex, 0); + write32(&exynos_clock->clk_src_kfc, SRC_KFC_HPM_SEL); + write32(&exynos_clock->clk_div_cpu1, HPM_RATIO); + write32(&exynos_clock->clk_div_cpu0, CLK_DIV_CPU0_VAL); /* switch A15 clock source to OSC clock before changing APLL */ clrbits_le32(&exynos_clock->clk_src_cpu, APLL_FOUT); /* Set APLL */ - writel(APLL_CON1_VAL, &exynos_clock->apll_con1); + write32(&exynos_clock->apll_con1, APLL_CON1_VAL); val = set_pll(225, 3, 0); /* FOUT=1800MHz */ - writel(val, &exynos_clock->apll_con0); - while ((readl(&exynos_clock->apll_con0) & PLL_LOCKED) == 0) + write32(&exynos_clock->apll_con0, val); + while ((read32(&exynos_clock->apll_con0) & PLL_LOCKED) == 0) ; /* now it is safe to switch to APLL */ setbits_le32(&exynos_clock->clk_src_cpu, APLL_FOUT); - writel(SRC_KFC_HPM_SEL, &exynos_clock->clk_src_kfc); - writel(CLK_DIV_KFC_VAL, &exynos_clock->clk_div_kfc0); + write32(&exynos_clock->clk_src_kfc, SRC_KFC_HPM_SEL); + write32(&exynos_clock->clk_div_kfc0, CLK_DIV_KFC_VAL); /* switch A7 clock source to OSC clock before changing KPLL */ clrbits_le32(&exynos_clock->clk_src_kfc, KPLL_FOUT); /* Set KPLL*/ - writel(KPLL_CON1_VAL, &exynos_clock->kpll_con1); + write32(&exynos_clock->kpll_con1, KPLL_CON1_VAL); val = set_pll(0x190, 0x4, 0x2); - writel(val, &exynos_clock->kpll_con0); - while ((readl(&exynos_clock->kpll_con0) & PLL_LOCKED) == 0) + write32(&exynos_clock->kpll_con0, val); + while ((read32(&exynos_clock->kpll_con0) & PLL_LOCKED) == 0) ; /* now it is safe to switch to KPLL */ setbits_le32(&exynos_clock->clk_src_kfc, KPLL_FOUT); /* Set MPLL */ - writel(MPLL_CON1_VAL, &exynos_clock->mpll_con1); + write32(&exynos_clock->mpll_con1, MPLL_CON1_VAL); val = set_pll(0xc8, 0x3, 0x1); - writel(val, &exynos_clock->mpll_con0); - while ((readl(&exynos_clock->mpll_con0) & PLL_LOCKED) == 0) + write32(&exynos_clock->mpll_con0, val); + while ((read32(&exynos_clock->mpll_con0) & PLL_LOCKED) == 0) ; /* Set DPLL */ - writel(DPLL_CON1_VAL, &exynos_clock->dpll_con1); + write32(&exynos_clock->dpll_con1, DPLL_CON1_VAL); val = set_pll(0x190, 0x4, 0x2); - writel(val, &exynos_clock->dpll_con0); - while ((readl(&exynos_clock->dpll_con0) & PLL_LOCKED) == 0) + write32(&exynos_clock->dpll_con0, val); + while ((read32(&exynos_clock->dpll_con0) & PLL_LOCKED) == 0) ; /* Set EPLL */ - writel(EPLL_CON2_VAL, &exynos_clock->epll_con2); - writel(EPLL_CON1_VAL, &exynos_clock->epll_con1); + write32(&exynos_clock->epll_con2, EPLL_CON2_VAL); + write32(&exynos_clock->epll_con1, EPLL_CON1_VAL); val = set_pll(0x64, 0x2, 0x1); - writel(val, &exynos_clock->epll_con0); - while ((readl(&exynos_clock->epll_con0) & PLL_LOCKED) == 0) + write32(&exynos_clock->epll_con0, val); + while ((read32(&exynos_clock->epll_con0) & PLL_LOCKED) == 0) ; /* Set CPLL */ - writel(CPLL_CON1_VAL, &exynos_clock->cpll_con1); + write32(&exynos_clock->cpll_con1, CPLL_CON1_VAL); val = set_pll(0xde, 0x4, 0x1); - writel(val, &exynos_clock->cpll_con0); - while ((readl(&exynos_clock->cpll_con0) & PLL_LOCKED) == 0) + write32(&exynos_clock->cpll_con0, val); + while ((read32(&exynos_clock->cpll_con0) & PLL_LOCKED) == 0) ; /* Set IPLL */ - writel(IPLL_CON1_VAL, &exynos_clock->ipll_con1); + write32(&exynos_clock->ipll_con1, IPLL_CON1_VAL); val = set_pll(0xB9, 0x3, 0x2); - writel(val, &exynos_clock->ipll_con0); - while ((readl(&exynos_clock->ipll_con0) & PLL_LOCKED) == 0) + write32(&exynos_clock->ipll_con0, val); + while ((read32(&exynos_clock->ipll_con0) & PLL_LOCKED) == 0) ; /* Set VPLL */ - writel(VPLL_CON1_VAL, &exynos_clock->vpll_con1); + write32(&exynos_clock->vpll_con1, VPLL_CON1_VAL); val = set_pll(0xd7, 0x3, 0x2); - writel(val, &exynos_clock->vpll_con0); - while ((readl(&exynos_clock->vpll_con0) & PLL_LOCKED) == 0) + write32(&exynos_clock->vpll_con0, val); + while ((read32(&exynos_clock->vpll_con0) & PLL_LOCKED) == 0) ; /* Set BPLL */ - writel(BPLL_CON1_VAL, &exynos_clock->bpll_con1); + write32(&exynos_clock->bpll_con1, BPLL_CON1_VAL); val = set_pll(0xc8, 0x3, 0x1); - writel(val, &exynos_clock->bpll_con0); - while ((readl(&exynos_clock->bpll_con0) & PLL_LOCKED) == 0) + write32(&exynos_clock->bpll_con0, val); + while ((read32(&exynos_clock->bpll_con0) & PLL_LOCKED) == 0) ; /* Set SPLL */ - writel(SPLL_CON1_VAL, &exynos_clock->spll_con1); + write32(&exynos_clock->spll_con1, SPLL_CON1_VAL); val = set_pll(200, 0x3, 0x2); /* 400MHz */ - writel(val, &exynos_clock->spll_con0); - while ((readl(&exynos_clock->spll_con0) & PLL_LOCKED) == 0) + write32(&exynos_clock->spll_con0, val); + while ((read32(&exynos_clock->spll_con0) & PLL_LOCKED) == 0) ; /* We use RPLL as the source for FIMD video stream clock */ - writel(RPLL_CON1_VAL, &exynos_clock->rpll_con1); - writel(RPLL_CON2_VAL, &exynos_clock->rpll_con2); + write32(&exynos_clock->rpll_con1, RPLL_CON1_VAL); + write32(&exynos_clock->rpll_con2, RPLL_CON2_VAL); /* computed by gabe from first principles; u-boot is probably * wrong again */ val = set_pll(0xa0, 0x3, 0x2); - writel(val, &exynos_clock->rpll_con0); + write32(&exynos_clock->rpll_con0, val); /* note: this is a meaningless exercise. The hardware lock * detection does not work. So this just spins for some * time and is done. NO indication of success should attach * to this or any other spin on a con0 value. */ - while ((readl(&exynos_clock->rpll_con0) & PLL_LOCKED) == 0) + while ((read32(&exynos_clock->rpll_con0) & PLL_LOCKED) == 0) ; - writel(CLK_DIV_CDREX0_VAL, &exynos_clock->clk_div_cdrex0); - writel(CLK_DIV_CDREX1_VAL, &exynos_clock->clk_div_cdrex1); + write32(&exynos_clock->clk_div_cdrex0, CLK_DIV_CDREX0_VAL); + write32(&exynos_clock->clk_div_cdrex1, CLK_DIV_CDREX1_VAL); - writel(CLK_SRC_TOP0_VAL, &exynos_clock->clk_src_top0); - writel(CLK_SRC_TOP1_VAL, &exynos_clock->clk_src_top1); - writel(CLK_SRC_TOP2_VAL, &exynos_clock->clk_src_top2); - writel(CLK_SRC_TOP7_VAL, &exynos_clock->clk_src_top7); + write32(&exynos_clock->clk_src_top0, CLK_SRC_TOP0_VAL); + write32(&exynos_clock->clk_src_top1, CLK_SRC_TOP1_VAL); + write32(&exynos_clock->clk_src_top2, CLK_SRC_TOP2_VAL); + write32(&exynos_clock->clk_src_top7, CLK_SRC_TOP7_VAL); - writel(CLK_DIV_TOP0_VAL, &exynos_clock->clk_div_top0); - writel(CLK_DIV_TOP1_VAL, &exynos_clock->clk_div_top1); - writel(CLK_DIV_TOP2_VAL, &exynos_clock->clk_div_top2); + write32(&exynos_clock->clk_div_top0, CLK_DIV_TOP0_VAL); + write32(&exynos_clock->clk_div_top1, CLK_DIV_TOP1_VAL); + write32(&exynos_clock->clk_div_top2, CLK_DIV_TOP2_VAL); - writel(0, &exynos_clock->clk_src_top10); - writel(0, &exynos_clock->clk_src_top11); - writel(0, &exynos_clock->clk_src_top12); + write32(&exynos_clock->clk_src_top10, 0); + write32(&exynos_clock->clk_src_top11, 0); + write32(&exynos_clock->clk_src_top12, 0); - writel(CLK_SRC_TOP3_VAL, &exynos_clock->clk_src_top3); - writel(CLK_SRC_TOP4_VAL, &exynos_clock->clk_src_top4); - writel(CLK_SRC_TOP5_VAL, &exynos_clock->clk_src_top5); + write32(&exynos_clock->clk_src_top3, CLK_SRC_TOP3_VAL); + write32(&exynos_clock->clk_src_top4, CLK_SRC_TOP4_VAL); + write32(&exynos_clock->clk_src_top5, CLK_SRC_TOP5_VAL); /* DISP1 BLK CLK SELECTION */ - writel(CLK_SRC_DISP1_0_VAL, &exynos_clock->clk_src_disp10); - writel(CLK_DIV_DISP1_0_VAL, &exynos_clock->clk_div_disp10); + write32(&exynos_clock->clk_src_disp10, CLK_SRC_DISP1_0_VAL); + write32(&exynos_clock->clk_div_disp10, CLK_DIV_DISP1_0_VAL); /* AUDIO BLK */ - writel(AUDIO0_SEL_EPLL, &exynos_clock->clk_src_mau); - writel(DIV_MAU_VAL, &exynos_clock->clk_div_mau); + write32(&exynos_clock->clk_src_mau, AUDIO0_SEL_EPLL); + write32(&exynos_clock->clk_div_mau, DIV_MAU_VAL); /* FSYS */ - writel(CLK_SRC_FSYS0_VAL, &exynos_clock->clk_src_fsys); - writel(CLK_DIV_FSYS0_VAL, &exynos_clock->clk_div_fsys0); - writel(CLK_DIV_FSYS1_VAL, &exynos_clock->clk_div_fsys1); - writel(CLK_DIV_FSYS2_VAL, &exynos_clock->clk_div_fsys2); - - writel(CLK_SRC_ISP_VAL, &exynos_clock->clk_src_isp); - writel(CLK_DIV_ISP0_VAL, &exynos_clock->clk_div_isp0); - writel(CLK_DIV_ISP1_VAL, &exynos_clock->clk_div_isp1); - - writel(CLK_SRC_PERIC0_VAL, &exynos_clock->clk_src_peric0); - writel(CLK_SRC_PERIC1_VAL, &exynos_clock->clk_src_peric1); - - writel(CLK_DIV_PERIC0_VAL, &exynos_clock->clk_div_peric0); - writel(CLK_DIV_PERIC1_VAL, &exynos_clock->clk_div_peric1); - writel(CLK_DIV_PERIC2_VAL, &exynos_clock->clk_div_peric2); - writel(CLK_DIV_PERIC3_VAL, &exynos_clock->clk_div_peric3); - writel(CLK_DIV_PERIC4_VAL, &exynos_clock->clk_div_peric4); - - writel(CLK_DIV_CPERI1_VAL, &exynos_clock->clk_div_cperi1); - - writel(CLK_DIV2_RATIO, &exynos_clock->clkdiv2_ratio); - writel(CLK_DIV4_RATIO, &exynos_clock->clkdiv4_ratio); - writel(CLK_DIV_G2D, &exynos_clock->clk_div_g2d); - - writel(CLK_SRC_CPU_VAL, &exynos_clock->clk_src_cpu); - writel(CLK_SRC_TOP6_VAL, &exynos_clock->clk_src_top6); - writel(CLK_SRC_CDREX_VAL, &exynos_clock->clk_src_cdrex); - writel(CLK_SRC_KFC_VAL, &exynos_clock->clk_src_kfc); + write32(&exynos_clock->clk_src_fsys, CLK_SRC_FSYS0_VAL); + write32(&exynos_clock->clk_div_fsys0, CLK_DIV_FSYS0_VAL); + write32(&exynos_clock->clk_div_fsys1, CLK_DIV_FSYS1_VAL); + write32(&exynos_clock->clk_div_fsys2, CLK_DIV_FSYS2_VAL); + + write32(&exynos_clock->clk_src_isp, CLK_SRC_ISP_VAL); + write32(&exynos_clock->clk_div_isp0, CLK_DIV_ISP0_VAL); + write32(&exynos_clock->clk_div_isp1, CLK_DIV_ISP1_VAL); + + write32(&exynos_clock->clk_src_peric0, CLK_SRC_PERIC0_VAL); + write32(&exynos_clock->clk_src_peric1, CLK_SRC_PERIC1_VAL); + + write32(&exynos_clock->clk_div_peric0, CLK_DIV_PERIC0_VAL); + write32(&exynos_clock->clk_div_peric1, CLK_DIV_PERIC1_VAL); + write32(&exynos_clock->clk_div_peric2, CLK_DIV_PERIC2_VAL); + write32(&exynos_clock->clk_div_peric3, CLK_DIV_PERIC3_VAL); + write32(&exynos_clock->clk_div_peric4, CLK_DIV_PERIC4_VAL); + + write32(&exynos_clock->clk_div_cperi1, CLK_DIV_CPERI1_VAL); + + write32(&exynos_clock->clkdiv2_ratio, CLK_DIV2_RATIO); + write32(&exynos_clock->clkdiv4_ratio, CLK_DIV4_RATIO); + write32(&exynos_clock->clk_div_g2d, CLK_DIV_G2D); + + write32(&exynos_clock->clk_src_cpu, CLK_SRC_CPU_VAL); + write32(&exynos_clock->clk_src_top6, CLK_SRC_TOP6_VAL); + write32(&exynos_clock->clk_src_cdrex, CLK_SRC_CDREX_VAL); + write32(&exynos_clock->clk_src_kfc, CLK_SRC_KFC_VAL); } void clock_gate(void) diff --git a/src/soc/samsung/exynos5420/dmc_common.c b/src/soc/samsung/exynos5420/dmc_common.c index cb1546e61a..c6fe09d705 100644 --- a/src/soc/samsung/exynos5420/dmc_common.c +++ b/src/soc/samsung/exynos5420/dmc_common.c @@ -45,19 +45,19 @@ int dmc_config_zq(struct mem_timings *mem, val |= mem->zq_mode_dds << PHY_CON16_ZQ_MODE_DDS_SHIFT; val |= mem->zq_mode_term << PHY_CON16_ZQ_MODE_TERM_SHIFT; val |= ZQ_CLK_DIV_EN; - writel(val, &phy0_ctrl->phy_con16); - writel(val, &phy1_ctrl->phy_con16); + write32(&phy0_ctrl->phy_con16, val); + write32(&phy1_ctrl->phy_con16, val); /* Disable termination */ if (mem->zq_mode_noterm) val |= PHY_CON16_ZQ_MODE_NOTERM_MASK; - writel(val, &phy0_ctrl->phy_con16); - writel(val, &phy1_ctrl->phy_con16); + write32(&phy0_ctrl->phy_con16, val); + write32(&phy1_ctrl->phy_con16, val); /* ZQ_MANUAL_START: Enable */ val |= ZQ_MANUAL_STR; - writel(val, &phy0_ctrl->phy_con16); - writel(val, &phy1_ctrl->phy_con16); + write32(&phy0_ctrl->phy_con16, val); + write32(&phy1_ctrl->phy_con16, val); /* ZQ_MANUAL_START: Disable */ val &= ~ZQ_MANUAL_STR; @@ -67,22 +67,22 @@ int dmc_config_zq(struct mem_timings *mem, * we are looping for the ZQ_init to complete. */ i = ZQ_INIT_TIMEOUT; - while ((readl(&phy0_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) { + while ((read32(&phy0_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) { udelay(1); i--; } if (!i) return -1; - writel(val, &phy0_ctrl->phy_con16); + write32(&phy0_ctrl->phy_con16, val); i = ZQ_INIT_TIMEOUT; - while ((readl(&phy1_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) { + while ((read32(&phy1_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) { udelay(1); i--; } if (!i) return -1; - writel(val, &phy1_ctrl->phy_con16); + write32(&phy1_ctrl->phy_con16, val); return 0; } @@ -93,18 +93,18 @@ void update_reset_dll(struct exynos5_dmc *dmc, enum ddr_mode mode) if (mode == DDR_MODE_DDR3) { val = MEM_TERM_EN | PHY_TERM_EN | DMC_CTRL_SHGATE; - writel(val, &dmc->phycontrol0); + write32(&dmc->phycontrol0, val); } /* Update DLL Information: Force DLL Resynchronization */ - val = readl(&dmc->phycontrol0); + val = read32(&dmc->phycontrol0); val |= FP_RSYNC; - writel(val, &dmc->phycontrol0); + write32(&dmc->phycontrol0, val); /* Reset Force DLL Resynchronization */ - val = readl(&dmc->phycontrol0); + val = read32(&dmc->phycontrol0); val &= ~FP_RSYNC; - writel(val, &dmc->phycontrol0); + write32(&dmc->phycontrol0, val); } void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc) @@ -121,7 +121,7 @@ void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc) mask |= chip << DIRECT_CMD_CHIP_SHIFT; /* Sending NOP command */ - writel(DIRECT_CMD_NOP | mask, &dmc->directcmd); + write32(&dmc->directcmd, DIRECT_CMD_NOP | mask); /* * TODO(alim.akhtar@samsung.com): Do we need these @@ -132,15 +132,15 @@ void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc) /* Sending EMRS/MRS commands */ for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) { - writel(mem->direct_cmd_msr[i] | mask, - &dmc->directcmd); + write32(&dmc->directcmd, + mem->direct_cmd_msr[i] | mask); udelay(100); } if (mem->send_zq_init) { /* Sending ZQINIT command */ - writel(DIRECT_CMD_ZQINIT | mask, - &dmc->directcmd); + write32(&dmc->directcmd, + DIRECT_CMD_ZQINIT | mask); /* * FIXME: This was originally sdelay(10000) * in the imported u-boot code. That may have @@ -166,7 +166,7 @@ void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc) mask |= chip << DIRECT_CMD_CHIP_SHIFT; /* PALL (all banks precharge) CMD */ - writel(DIRECT_CMD_PALL | mask, &dmc->directcmd); + write32(&dmc->directcmd, DIRECT_CMD_PALL | mask); udelay(100); } } diff --git a/src/soc/samsung/exynos5420/dmc_init_ddr3.c b/src/soc/samsung/exynos5420/dmc_init_ddr3.c index 8186b6dbdf..6972618ac3 100644 --- a/src/soc/samsung/exynos5420/dmc_init_ddr3.c +++ b/src/soc/samsung/exynos5420/dmc_init_ddr3.c @@ -47,40 +47,40 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) /* Enable BYPASS mode */ setbits_le32(&exynos_clock->bpll_con1, BYPASS_EN); - writel(MUX_BPLL_SEL_FOUTBPLL, &exynos_clock->clk_src_cdrex); + write32(&exynos_clock->clk_src_cdrex, MUX_BPLL_SEL_FOUTBPLL); do { - val = readl(&exynos_clock->clk_mux_stat_cdrex); + val = read32(&exynos_clock->clk_mux_stat_cdrex); val &= BPLL_SEL_MASK; } while (val != FOUTBPLL); clrbits_le32(&exynos_clock->bpll_con1, BYPASS_EN); /* Specify the DDR memory type as DDR3 */ - val = readl(&exynos_phy0_control->phy_con0); + val = read32(&exynos_phy0_control->phy_con0); val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT); val |= (mem->mem_type << PHY_CON0_CTRL_DDR_MODE_SHIFT); - writel(val, &exynos_phy0_control->phy_con0); + write32(&exynos_phy0_control->phy_con0, val); - val = readl(&exynos_phy1_control->phy_con0); + val = read32(&exynos_phy1_control->phy_con0); val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT); val |= (mem->mem_type << PHY_CON0_CTRL_DDR_MODE_SHIFT); - writel(val, &exynos_phy1_control->phy_con0); + write32(&exynos_phy1_control->phy_con0, val); /* Set Read Latency and Burst Length for PHY0 and PHY1 */ val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) | (mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT); - writel(val, &exynos_phy0_control->phy_con42); - writel(val, &exynos_phy1_control->phy_con42); + write32(&exynos_phy0_control->phy_con42, val); + write32(&exynos_phy1_control->phy_con42, val); - val = readl(&exynos_phy0_control->phy_con26); + val = read32(&exynos_phy0_control->phy_con26); val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET); val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET); - writel(val, &exynos_phy0_control->phy_con26); + write32(&exynos_phy0_control->phy_con26, val); - val = readl(&exynos_phy1_control->phy_con26); + val = read32(&exynos_phy1_control->phy_con26); val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET); val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET); - writel(val, &exynos_phy1_control->phy_con26); + write32(&exynos_phy1_control->phy_con26, val); /* Set Driver strength for CK, CKE, CS & CA to 0x7 * Set Driver strength for Data Slice 0~3 to 0x6 @@ -89,8 +89,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) (0x7 << CA_CS_DRVR_DS_OFFSET) | (0x7 << CA_ADR_DRVR_DS_OFFSET); val |= (0x7 << DA_3_DS_OFFSET) | (0x7 << DA_2_DS_OFFSET) | (0x7 << DA_1_DS_OFFSET) | (0x7 << DA_0_DS_OFFSET); - writel(val, &exynos_phy0_control->phy_con39); - writel(val, &exynos_phy1_control->phy_con39); + write32(&exynos_phy0_control->phy_con39, val); + write32(&exynos_phy1_control->phy_con39, val); /* ZQ Calibration */ if (dmc_config_zq(mem, exynos_phy0_control, exynos_phy1_control)) @@ -100,31 +100,27 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) clrbits_le32(&exynos_phy1_control->phy_con16, ZQ_CLK_DIV_EN); /* DQ Signal */ - val = readl(&exynos_phy0_control->phy_con14); + val = read32(&exynos_phy0_control->phy_con14); val |= mem->phy0_pulld_dqs; - writel(val, &exynos_phy0_control->phy_con14); - val = readl(&exynos_phy1_control->phy_con14); + write32(&exynos_phy0_control->phy_con14, val); + val = read32(&exynos_phy1_control->phy_con14); val |= mem->phy1_pulld_dqs; - writel(val, &exynos_phy1_control->phy_con14); + write32(&exynos_phy1_control->phy_con14, val); val = MEM_TERM_EN | PHY_TERM_EN; - writel(val, &exynos_drex0->phycontrol0); - writel(val, &exynos_drex1->phycontrol0); - - writel(mem->concontrol | - (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) | - (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT), - &exynos_drex0->concontrol); - writel(mem->concontrol | - (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) | - (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT), - &exynos_drex1->concontrol); + write32(&exynos_drex0->phycontrol0, val); + write32(&exynos_drex1->phycontrol0, val); + + write32(&exynos_drex0->concontrol, + mem->concontrol | (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)); + write32(&exynos_drex1->concontrol, + mem->concontrol | (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)); do { - val = readl(&exynos_drex0->phystatus); + val = read32(&exynos_drex0->phystatus); } while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE); do { - val = readl(&exynos_drex1->phystatus); + val = read32(&exynos_drex1->phystatus); } while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE); clrbits_le32(&exynos_drex0->concontrol, DFI_INIT_START); @@ -134,41 +130,41 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) update_reset_dll(exynos_drex1, mem->mem_type); /* MEMBASECONFIG0 (CS0) */ - writel(mem->membaseconfig0, &exynos_tzasc0->membaseconfig0); - writel(mem->membaseconfig0, &exynos_tzasc1->membaseconfig0); + write32(&exynos_tzasc0->membaseconfig0, mem->membaseconfig0); + write32(&exynos_tzasc1->membaseconfig0, mem->membaseconfig0); /* MEMBASECONFIG1 (CS1) */ if (mem->chips_per_channel == 2) { - writel(mem->membaseconfig1, &exynos_tzasc0->membaseconfig1); - writel(mem->membaseconfig1, &exynos_tzasc1->membaseconfig1); + write32(&exynos_tzasc0->membaseconfig1, mem->membaseconfig1); + write32(&exynos_tzasc1->membaseconfig1, mem->membaseconfig1); } /* Memory Channel Interleaving Size * Exynos5420 Channel interleaving = 128 bytes */ /* MEMCONFIG0/1 */ - writel(mem->memconfig, &exynos_tzasc0->memconfig0); - writel(mem->memconfig, &exynos_tzasc1->memconfig0); - writel(mem->memconfig, &exynos_tzasc0->memconfig1); - writel(mem->memconfig, &exynos_tzasc1->memconfig1); + write32(&exynos_tzasc0->memconfig0, mem->memconfig); + write32(&exynos_tzasc1->memconfig0, mem->memconfig); + write32(&exynos_tzasc0->memconfig1, mem->memconfig); + write32(&exynos_tzasc1->memconfig1, mem->memconfig); /* Precharge Configuration */ - writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT, - &exynos_drex0->prechconfig0); - writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT, - &exynos_drex1->prechconfig0); + write32(&exynos_drex0->prechconfig0, + mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT); + write32(&exynos_drex1->prechconfig0, + mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT); /* TimingRow, TimingData, TimingPower and Timingref * values as per Memory AC parameters */ - writel(mem->timing_ref, &exynos_drex0->timingref); - writel(mem->timing_ref, &exynos_drex1->timingref); - writel(mem->timing_row, &exynos_drex0->timingrow); - writel(mem->timing_row, &exynos_drex1->timingrow); - writel(mem->timing_data, &exynos_drex0->timingdata); - writel(mem->timing_data, &exynos_drex1->timingdata); - writel(mem->timing_power, &exynos_drex0->timingpower); - writel(mem->timing_power, &exynos_drex1->timingpower); + write32(&exynos_drex0->timingref, mem->timing_ref); + write32(&exynos_drex1->timingref, mem->timing_ref); + write32(&exynos_drex0->timingrow, mem->timing_row); + write32(&exynos_drex1->timingrow, mem->timing_row); + write32(&exynos_drex0->timingdata, mem->timing_data); + write32(&exynos_drex1->timingdata, mem->timing_data); + write32(&exynos_drex0->timingpower, mem->timing_power); + write32(&exynos_drex1->timingpower, mem->timing_power); if (reset) { /* Send NOP, MRS and ZQINIT commands. @@ -189,8 +185,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) * release pad retention and retain the memory content until the * initialization is complete. */ - writel(PAD_RETENTION_DRAM_COREBLK_VAL, - &exynos_power->padret_dram_cblk_opt); + write32(&exynos_power->padret_dram_cblk_opt, + PAD_RETENTION_DRAM_COREBLK_VAL); do { ret = read32(&exynos_power->padret_dram_status); } while (ret != 0x1); @@ -201,57 +197,55 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) */ for (i = 0; i < 128; i++) { for (chip = 0; chip < mem->chips_to_configure; chip++) { - writel(DIRECT_CMD_REFA | - (chip << DIRECT_CMD_CHIP_SHIFT), - &exynos_drex0->directcmd); - writel(DIRECT_CMD_REFA | - (chip << DIRECT_CMD_CHIP_SHIFT), - &exynos_drex1->directcmd); + write32(&exynos_drex0->directcmd, + DIRECT_CMD_REFA | (chip << DIRECT_CMD_CHIP_SHIFT)); + write32(&exynos_drex1->directcmd, + DIRECT_CMD_REFA | (chip << DIRECT_CMD_CHIP_SHIFT)); } } } if (mem->gate_leveling_enable) { - writel(PHY_CON0_RESET_VAL, &exynos_phy0_control->phy_con0); - writel(PHY_CON0_RESET_VAL, &exynos_phy1_control->phy_con0); + write32(&exynos_phy0_control->phy_con0, PHY_CON0_RESET_VAL); + write32(&exynos_phy1_control->phy_con0, PHY_CON0_RESET_VAL); setbits_le32(&exynos_phy0_control->phy_con0, P0_CMD_EN); setbits_le32(&exynos_phy1_control->phy_con0, P0_CMD_EN); val = PHY_CON2_RESET_VAL; val |= INIT_DESKEW_EN; - writel(val, &exynos_phy0_control->phy_con2); - writel(val, &exynos_phy1_control->phy_con2); + write32(&exynos_phy0_control->phy_con2, val); + write32(&exynos_phy1_control->phy_con2, val); - val = readl(&exynos_phy0_control->phy_con1); + val = read32(&exynos_phy0_control->phy_con1); val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET); - writel(val, &exynos_phy0_control->phy_con1); + write32(&exynos_phy0_control->phy_con1, val); - val = readl(&exynos_phy1_control->phy_con1); + val = read32(&exynos_phy1_control->phy_con1); val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET); - writel(val, &exynos_phy1_control->phy_con1); + write32(&exynos_phy1_control->phy_con1, val); - nLockR = readl(&exynos_phy0_control->phy_con13); + nLockR = read32(&exynos_phy0_control->phy_con13); nLockW_phy0 = (nLockR & CTRL_LOCK_COARSE_MASK) >> 2; - nLockR = readl(&exynos_phy0_control->phy_con12); + nLockR = read32(&exynos_phy0_control->phy_con12); nLockR &= ~CTRL_DLL_ON; nLockR |= nLockW_phy0; - writel(nLockR, &exynos_phy0_control->phy_con12); + write32(&exynos_phy0_control->phy_con12, nLockR); - nLockR = readl(&exynos_phy1_control->phy_con13); + nLockR = read32(&exynos_phy1_control->phy_con13); nLockW_phy1 = (nLockR & CTRL_LOCK_COARSE_MASK) >> 2; - nLockR = readl(&exynos_phy1_control->phy_con12); + nLockR = read32(&exynos_phy1_control->phy_con12); nLockR &= ~CTRL_DLL_ON; nLockR |= nLockW_phy1; - writel(nLockR, &exynos_phy1_control->phy_con12); + write32(&exynos_phy1_control->phy_con12, nLockR); val = (0x3 << DIRECT_CMD_BANK_SHIFT) | 0x4; for (chip = 0; chip < mem->chips_to_configure; chip++) { - writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), - &exynos_drex0->directcmd); - writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), - &exynos_drex1->directcmd); + write32(&exynos_drex0->directcmd, + val | (chip << DIRECT_CMD_CHIP_SHIFT)); + write32(&exynos_drex1->directcmd, + val | (chip << DIRECT_CMD_CHIP_SHIFT)); } setbits_le32(&exynos_phy0_control->phy_con2, RDLVL_GATE_EN); @@ -260,17 +254,17 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) setbits_le32(&exynos_phy0_control->phy_con0, CTRL_SHGATE); setbits_le32(&exynos_phy1_control->phy_con0, CTRL_SHGATE); - val = readl(&exynos_phy0_control->phy_con1); + val = read32(&exynos_phy0_control->phy_con1); val &= ~(CTRL_GATEDURADJ_MASK); - writel(val, &exynos_phy0_control->phy_con1); + write32(&exynos_phy0_control->phy_con1, val); - val = readl(&exynos_phy1_control->phy_con1); + val = read32(&exynos_phy1_control->phy_con1); val &= ~(CTRL_GATEDURADJ_MASK); - writel(val, &exynos_phy1_control->phy_con1); + write32(&exynos_phy1_control->phy_con1, val); - writel(CTRL_RDLVL_GATE_ENABLE, &exynos_drex0->rdlvl_config); + write32(&exynos_drex0->rdlvl_config, CTRL_RDLVL_GATE_ENABLE); i = TIMEOUT; - while (((readl(&exynos_drex0->phystatus) & RDLVL_COMPLETE_CHO) + while (((read32(&exynos_drex0->phystatus) & RDLVL_COMPLETE_CHO) != RDLVL_COMPLETE_CHO) && (i > 0)) { /* * TODO(waihong): Comment on how long this take to @@ -281,11 +275,11 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) } if (!i) return SETUP_ERR_RDLV_COMPLETE_TIMEOUT; - writel(CTRL_RDLVL_GATE_DISABLE, &exynos_drex0->rdlvl_config); + write32(&exynos_drex0->rdlvl_config, CTRL_RDLVL_GATE_DISABLE); - writel(CTRL_RDLVL_GATE_ENABLE, &exynos_drex1->rdlvl_config); + write32(&exynos_drex1->rdlvl_config, CTRL_RDLVL_GATE_ENABLE); i = TIMEOUT; - while (((readl(&exynos_drex1->phystatus) & RDLVL_COMPLETE_CHO) + while (((read32(&exynos_drex1->phystatus) & RDLVL_COMPLETE_CHO) != RDLVL_COMPLETE_CHO) && (i > 0)) { /* * TODO(waihong): Comment on how long this take to @@ -296,23 +290,23 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) } if (!i) return SETUP_ERR_RDLV_COMPLETE_TIMEOUT; - writel(CTRL_RDLVL_GATE_DISABLE, &exynos_drex1->rdlvl_config); + write32(&exynos_drex1->rdlvl_config, CTRL_RDLVL_GATE_DISABLE); - writel(0, &exynos_phy0_control->phy_con14); - writel(0, &exynos_phy1_control->phy_con14); + write32(&exynos_phy0_control->phy_con14, 0); + write32(&exynos_phy1_control->phy_con14, 0); val = (0x3 << DIRECT_CMD_BANK_SHIFT); for (chip = 0; chip < mem->chips_to_configure; chip++) { - writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), - &exynos_drex0->directcmd); - writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), - &exynos_drex1->directcmd); + write32(&exynos_drex0->directcmd, + val | (chip << DIRECT_CMD_CHIP_SHIFT)); + write32(&exynos_drex1->directcmd, + val | (chip << DIRECT_CMD_CHIP_SHIFT)); } /* Common Settings for Leveling */ val = PHY_CON12_RESET_VAL; - writel((val + nLockW_phy0), &exynos_phy0_control->phy_con12); - writel((val + nLockW_phy1), &exynos_phy1_control->phy_con12); + write32(&exynos_phy0_control->phy_con12, (val + nLockW_phy0)); + write32(&exynos_phy1_control->phy_con12, (val + nLockW_phy1)); setbits_le32(&exynos_phy0_control->phy_con2, DLL_DESKEW_EN); setbits_le32(&exynos_phy1_control->phy_con2, DLL_DESKEW_EN); @@ -322,22 +316,18 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) dmc_config_prech(mem, exynos_drex0); dmc_config_prech(mem, exynos_drex1); - writel(mem->memcontrol, &exynos_drex0->memcontrol); - writel(mem->memcontrol, &exynos_drex1->memcontrol); + write32(&exynos_drex0->memcontrol, mem->memcontrol); + write32(&exynos_drex1->memcontrol, mem->memcontrol); /* * Set DMC Concontrol: Enable auto-refresh counter, provide * read data fetch cycles and enable DREX auto set powerdown * for input buffer of I/O in none read memory state. */ - writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) | - (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)| - DMC_CONCONTROL_IO_PD_CON(0x2), - &exynos_drex0->concontrol); - writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) | - (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)| - DMC_CONCONTROL_IO_PD_CON(0x2), - &exynos_drex1->concontrol); + write32(&exynos_drex0->concontrol, + mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) | DMC_CONCONTROL_IO_PD_CON(0x2)); + write32(&exynos_drex1->concontrol, + mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) | DMC_CONCONTROL_IO_PD_CON(0x2)); /* Enable Clock Gating Control for DMC * this saves around 25 mw dmc power as compared to the power diff --git a/src/soc/samsung/exynos5420/dp_lowlevel.c b/src/soc/samsung/exynos5420/dp_lowlevel.c index 5a3adf907e..f56148fec3 100644 --- a/src/soc/samsung/exynos5420/dp_lowlevel.c +++ b/src/soc/samsung/exynos5420/dp_lowlevel.c @@ -55,7 +55,7 @@ static inline unsigned long fradl(void *v) { #define lread32(a) fradl((void *)(a)) #else -#define lwrite32(a,b) writel((unsigned long)(a), (void *)(b)) +#define lwrite32(a,b) write32((void *)(b), (unsigned long)(a)) #define lread32(a) read32((void *)(a)) #endif diff --git a/src/soc/samsung/exynos5420/fimd.c b/src/soc/samsung/exynos5420/fimd.c index dfd123254c..8059f49f1a 100644 --- a/src/soc/samsung/exynos5420/fimd.c +++ b/src/soc/samsung/exynos5420/fimd.c @@ -47,8 +47,8 @@ static inline unsigned long fradl(void *v) { #define lreadl(a) fradl((void *)(a)) #else -#define lwritel(a,b) writel((unsigned long)(a), (void *)(b)) -#define lreadl(a) readl((void *)(a)) +#define lwritel(a,b) write32((void *)(b), (unsigned long)(a)) +#define lreadl(a) read32((void *)(a)) #endif /* not sure where we want this so ... */ diff --git a/src/soc/samsung/exynos5420/gpio.c b/src/soc/samsung/exynos5420/gpio.c index 92cdc28fc0..0a53018b3f 100644 --- a/src/soc/samsung/exynos5420/gpio.c +++ b/src/soc/samsung/exynos5420/gpio.c @@ -82,10 +82,10 @@ void gpio_cfg_pin(int gpio, int cfg) unsigned int value; struct gpio_bank *bank = gpio_get_bank(gpio); - value = readl(&bank->con); + value = read32(&bank->con); value &= ~CON_MASK(GPIO_BIT(gpio)); value |= CON_SFR(GPIO_BIT(gpio), cfg); - writel(value, &bank->con); + write32(&bank->con, value); } static int gpio_get_cfg(int gpio) @@ -93,7 +93,7 @@ static int gpio_get_cfg(int gpio) struct gpio_bank *bank = gpio_get_bank(gpio); int shift = GPIO_BIT(gpio) << 2; - return (readl(&bank->con) & CON_MASK(GPIO_BIT(gpio))) >> shift; + return (read32(&bank->con) & CON_MASK(GPIO_BIT(gpio))) >> shift; } void gpio_set_pull(int gpio, int mode) @@ -101,7 +101,7 @@ void gpio_set_pull(int gpio, int mode) unsigned int value; struct gpio_bank *bank = gpio_get_bank(gpio); - value = readl(&bank->pull); + value = read32(&bank->pull); value &= ~PULL_MASK(GPIO_BIT(gpio)); switch (mode) { @@ -113,7 +113,7 @@ void gpio_set_pull(int gpio, int mode) break; } - writel(value, &bank->pull); + write32(&bank->pull, value); } void gpio_set_drv(int gpio, int mode) @@ -121,7 +121,7 @@ void gpio_set_drv(int gpio, int mode) unsigned int value; struct gpio_bank *bank = gpio_get_bank(gpio); - value = readl(&bank->drv); + value = read32(&bank->drv); value &= ~DRV_MASK(GPIO_BIT(gpio)); switch (mode) { @@ -135,7 +135,7 @@ void gpio_set_drv(int gpio, int mode) return; } - writel(value, &bank->drv); + write32(&bank->drv, value); } void gpio_set_rate(int gpio, int mode) @@ -143,7 +143,7 @@ void gpio_set_rate(int gpio, int mode) unsigned int value; struct gpio_bank *bank = gpio_get_bank(gpio); - value = readl(&bank->drv); + value = read32(&bank->drv); value &= ~RATE_MASK(GPIO_BIT(gpio)); switch (mode) { @@ -155,7 +155,7 @@ void gpio_set_rate(int gpio, int mode) return; } - writel(value, &bank->drv); + write32(&bank->drv, value); } int gpio_direction_input(unsigned gpio) @@ -170,11 +170,11 @@ int gpio_direction_output(unsigned gpio, int value) unsigned int val; struct gpio_bank *bank = gpio_get_bank(gpio); - val = readl(&bank->dat); + val = read32(&bank->dat); val &= ~DAT_MASK(GPIO_BIT(gpio)); if (value) val |= DAT_SET(GPIO_BIT(gpio)); - writel(val, &bank->dat); + write32(&bank->dat, val); gpio_cfg_pin(gpio, GPIO_OUTPUT); @@ -186,7 +186,7 @@ int gpio_get_value(unsigned gpio) unsigned int value; struct gpio_bank *bank = gpio_get_bank(gpio); - value = readl(&bank->dat); + value = read32(&bank->dat); return !!(value & DAT_MASK(GPIO_BIT(gpio))); } @@ -195,11 +195,11 @@ int gpio_set_value(unsigned gpio, int value) unsigned int val; struct gpio_bank *bank = gpio_get_bank(gpio); - val = readl(&bank->dat); + val = read32(&bank->dat); val &= ~DAT_MASK(GPIO_BIT(gpio)); if (value) val |= DAT_SET(GPIO_BIT(gpio)); - writel(val, &bank->dat); + write32(&bank->dat, val); return 0; } diff --git a/src/soc/samsung/exynos5420/i2c.c b/src/soc/samsung/exynos5420/i2c.c index 28e3f0c331..1b541b7326 100644 --- a/src/soc/samsung/exynos5420/i2c.c +++ b/src/soc/samsung/exynos5420/i2c.c @@ -270,7 +270,7 @@ static int hsi2c_get_clk_details(struct i2c_bus *i2c, int *div, int *cycle, * temp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) * temp1 = (TSCLK_L + TSCLK_H + 2) */ - uint32_t flt_cycle = (readl(®s->i2c_conf) >> 16) & 0x7; + uint32_t flt_cycle = (read32(®s->i2c_conf) >> 16) & 0x7; int temp = (clkin / op_clk) - 8 - 2 * flt_cycle; // CLK_DIV max is 256. @@ -310,18 +310,18 @@ static void hsi2c_ch_init(struct i2c_bus *i2c, unsigned int frequency) uint32_t timing_sla = data_hd << 0; // Currently operating in fast speed mode. - writel(timing_fs1, ®s->i2c_timing_fs1); - writel(timing_fs2, ®s->i2c_timing_fs2); - writel(timing_fs3, ®s->i2c_timing_fs3); - writel(timing_sla, ®s->i2c_timing_sla); + write32(®s->i2c_timing_fs1, timing_fs1); + write32(®s->i2c_timing_fs2, timing_fs2); + write32(®s->i2c_timing_fs3, timing_fs3); + write32(®s->i2c_timing_sla, timing_sla); // Clear to enable timeout. - writel(readl(®s->i2c_timeout) & ~Hsi2cTimeoutEn, - ®s->i2c_timeout); + write32(®s->i2c_timeout, + read32(®s->i2c_timeout) & ~Hsi2cTimeoutEn); - writel(Hsi2cTrailingCount, ®s->usi_trailing_ctl); - writel(Hsi2cRxfifoEn | Hsi2cTxfifoEn, ®s->usi_fifo_ctl); - writel(readl(®s->i2c_conf) | Hsi2cAutoMode, ®s->i2c_conf); + write32(®s->usi_trailing_ctl, Hsi2cTrailingCount); + write32(®s->usi_fifo_ctl, Hsi2cRxfifoEn | Hsi2cTxfifoEn); + write32(®s->i2c_conf, read32(®s->i2c_conf) | Hsi2cAutoMode); } static void hsi2c_reset(struct i2c_bus *i2c) @@ -329,8 +329,8 @@ static void hsi2c_reset(struct i2c_bus *i2c) struct hsi2c_regs *regs = i2c->hsregs; // Set and clear the bit for reset. - writel(readl(®s->usi_ctl) | Hsi2cSwRst, ®s->usi_ctl); - writel(readl(®s->usi_ctl) & ~Hsi2cSwRst, ®s->usi_ctl); + write32(®s->usi_ctl, read32(®s->usi_ctl) | Hsi2cSwRst); + write32(®s->usi_ctl, read32(®s->usi_ctl) & ~Hsi2cSwRst); /* FIXME: This just assumes 100KHz as a default bus freq */ hsi2c_ch_init(i2c, 100000); @@ -356,13 +356,13 @@ static void i2c_ch_init(struct i2c_bus *i2c, int speed) // Set prescaler, divisor according to freq, also set ACKGEN, IRQ. val = (div & 0x0f) | 0xa0 | ((pres == 512) ? 0x40 : 0); - writel(val, ®s->con); + write32(®s->con, val); // Init to SLAVE RECEIVE mode and clear I2CADDn. - writel(0, ®s->stat); - writel(0, ®s->add); + write32(®s->stat, 0); + write32(®s->add, 0); // program Master Transmit (and implicit STOP). - writel(I2cStatMasterXmit | I2cStatEnable, ®s->stat); + write32(®s->stat, I2cStatMasterXmit | I2cStatEnable); } void i2c_init(unsigned bus, int speed, int slaveadd) @@ -430,7 +430,7 @@ static int hsi2c_senddata(struct hsi2c_regs *regs, const uint8_t *data, int len) { while (!hsi2c_check_transfer(regs) && len) { if (!(read32(®s->usi_fifo_stat) & Hsi2cTxFifoFull)) { - writel(*data++, ®s->usi_txdata); + write32(®s->usi_txdata, *data++); len--; } } @@ -452,7 +452,7 @@ static int hsi2c_segment(struct i2c_seg *seg, struct hsi2c_regs *regs, int stop) { const uint32_t usi_ctl = Hsi2cFuncModeI2c | Hsi2cMaster; - writel(HSI2C_SLV_ADDR_MAS(seg->chip), ®s->i2c_addr); + write32(®s->i2c_addr, HSI2C_SLV_ADDR_MAS(seg->chip)); /* * We really only want to stop after this transaction (I think) if the @@ -465,14 +465,14 @@ static int hsi2c_segment(struct i2c_seg *seg, struct hsi2c_regs *regs, int stop) seg->len | Hsi2cMasterRun | Hsi2cStopAfterTrans; if (seg->read) { - writel(usi_ctl | Hsi2cRxchon, ®s->usi_ctl); - writel(autoconf | Hsi2cReadWrite, ®s->i2c_auto_conf); + write32(®s->usi_ctl, usi_ctl | Hsi2cRxchon); + write32(®s->i2c_auto_conf, autoconf | Hsi2cReadWrite); if (hsi2c_recvdata(regs, seg->buf, seg->len)) return -1; } else { - writel(usi_ctl | Hsi2cTxchon, ®s->usi_ctl); - writel(autoconf, ®s->i2c_auto_conf); + write32(®s->usi_ctl, usi_ctl | Hsi2cTxchon); + write32(®s->i2c_auto_conf, autoconf); if (hsi2c_senddata(regs, seg->buf, seg->len)) return -1; @@ -481,7 +481,7 @@ static int hsi2c_segment(struct i2c_seg *seg, struct hsi2c_regs *regs, int stop) if (hsi2c_wait_for_transfer(regs) != 1) return -1; - writel(Hsi2cFuncModeI2c, ®s->usi_ctl); + write32(®s->usi_ctl, Hsi2cFuncModeI2c); return 0; } @@ -510,34 +510,34 @@ static int hsi2c_transfer(struct i2c_bus *i2c, struct i2c_seg *segments, static int i2c_int_pending(struct i2c_regs *regs) { - return readb(®s->con) & I2cConIntPending; + return read8(®s->con) & I2cConIntPending; } static void i2c_clear_int(struct i2c_regs *regs) { - writeb(readb(®s->con) & ~I2cConIntPending, ®s->con); + write8(®s->con, read8(®s->con) & ~I2cConIntPending); } static void i2c_ack_enable(struct i2c_regs *regs) { - writeb(readb(®s->con) | I2cConAckGen, ®s->con); + write8(®s->con, read8(®s->con) | I2cConAckGen); } static void i2c_ack_disable(struct i2c_regs *regs) { - writeb(readb(®s->con) & ~I2cConAckGen, ®s->con); + write8(®s->con, read8(®s->con) & ~I2cConAckGen); } static int i2c_got_ack(struct i2c_regs *regs) { - return !(readb(®s->stat) & I2cStatAck); + return !(read8(®s->stat) & I2cStatAck); } static int i2c_wait_for_idle(struct i2c_regs *regs) { int timeout = 1000 * 100; // 1s. while (timeout--) { - if (!(readb(®s->stat) & I2cStatBusy)) + if (!(read8(®s->stat) & I2cStatBusy)) return 0; udelay(10); } @@ -562,17 +562,17 @@ static int i2c_wait_for_int(struct i2c_regs *regs) static int i2c_send_stop(struct i2c_regs *regs) { - uint8_t mode = readb(®s->stat) & (I2cStatModeMask); - writeb(mode | I2cStatEnable, ®s->stat); + uint8_t mode = read8(®s->stat) & (I2cStatModeMask); + write8(®s->stat, mode | I2cStatEnable); i2c_clear_int(regs); return i2c_wait_for_idle(regs); } static int i2c_send_start(struct i2c_regs *regs, int read, int chip) { - writeb(chip << 1, ®s->ds); + write8(®s->ds, chip << 1); uint8_t mode = read ? I2cStatMasterRecv : I2cStatMasterXmit; - writeb(mode | I2cStatStartStop | I2cStatEnable, ®s->stat); + write8(®s->stat, mode | I2cStatStartStop | I2cStatEnable); i2c_clear_int(regs); if (i2c_wait_for_int(regs)) @@ -594,7 +594,7 @@ static int i2c_xmit_buf(struct i2c_regs *regs, uint8_t *data, int len) int i; for (i = 0; i < len; i++) { - writeb(data[i], ®s->ds); + write8(®s->ds, data[i]); i2c_clear_int(regs); if (i2c_wait_for_int(regs)) @@ -624,7 +624,7 @@ static int i2c_recv_buf(struct i2c_regs *regs, uint8_t *data, int len) if (i2c_wait_for_int(regs)) return 1; - data[i] = readb(®s->ds); + data[i] = read8(®s->ds); } return 0; @@ -642,7 +642,7 @@ int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count) if (!regs || i2c_wait_for_idle(regs)) return 1; - writeb(I2cStatMasterXmit | I2cStatEnable, ®s->stat); + write8(®s->stat, I2cStatMasterXmit | I2cStatEnable); int i; for (i = 0; i < count; i++) { diff --git a/src/soc/samsung/exynos5420/power.c b/src/soc/samsung/exynos5420/power.c index c7d491dd23..1b8aaa67d1 100644 --- a/src/soc/samsung/exynos5420/power.c +++ b/src/soc/samsung/exynos5420/power.c @@ -89,5 +89,5 @@ void power_enable_xclkout(void) void power_release_uart_retention(void) { - writel(1 << 28, &exynos_power->padret_uart_opt); + write32(&exynos_power->padret_uart_opt, 1 << 28); } diff --git a/src/soc/samsung/exynos5420/smp.c b/src/soc/samsung/exynos5420/smp.c index 8775bc9baf..6c8fd06f20 100644 --- a/src/soc/samsung/exynos5420/smp.c +++ b/src/soc/samsung/exynos5420/smp.c @@ -152,7 +152,7 @@ static void enable_smp(void) actlr |= ACTLR_SMP; /* Dummy read to assure L2 access */ - val = readl(&exynos_power->inform0); + val = read32(&exynos_power->inform0); val &= 0; actlr |= val; @@ -200,9 +200,9 @@ static void low_power_start(void) /* On warm reset, because iRAM is not cleared, all cores will enter * low_power_start, not the initial address. So we need to check reset * status again, and jump to 0x0 in that case. */ - reg_val = readl(&exynos_power->spare0); + reg_val = read32(&exynos_power->spare0); if (reg_val != RST_FLAG_VAL) { - writel(0x0, VECTOR_LOW_POWER_FLAG); + write32(VECTOR_LOW_POWER_FLAG, 0x0); jump_bx(CORE_RESET_INIT_ADDRESS); /* restart cpu execution and never returns. */ } @@ -211,9 +211,9 @@ static void low_power_start(void) * path, bypassing first jump address and makes final jump address 0x0, * so we try to make any core set again low_power_start address, if that * becomes zero. */ - reg_val = readl(VECTOR_CORE_SEV_HANDLER); + reg_val = read32(VECTOR_CORE_SEV_HANDLER); if (reg_val != (intptr_t)low_power_start) { - writel((intptr_t)low_power_start, VECTOR_CORE_SEV_HANDLER); + write32(VECTOR_CORE_SEV_HANDLER, (intptr_t)low_power_start); dsb(); /* ask all cores to power on again. */ sev(); @@ -258,7 +258,7 @@ static void power_down_core(void) * S5E5420A User Manual, 8.8.1.202, ARM_CORE0_CONFIGURATION, two bits to * control power state in each power down level. */ - writel(0x0, &exynos_power->arm_core[core_id].config); + write32(&exynos_power->arm_core[core_id].config, 0x0); /* S5E5420A User Manual, 8.4.2.5, after ARM_CORE*_CONFIGURATION has been * set to zero, PMU will detect and wait for WFI then run power-down @@ -281,15 +281,15 @@ static void configure_secondary_cores(void) * when we want to use SMP inside firmware. */ /* Clear boot reg (hotplug address) in cpu states */ - writel(0, (void*)&exynos_cpu_states->hotplug_address); + write32((void *)&exynos_cpu_states->hotplug_address, 0); /* set low_power flag and address */ - writel((intptr_t)low_power_start, VECTOR_LOW_POWER_ADDRESS); - writel(RST_FLAG_VAL, VECTOR_LOW_POWER_FLAG); - writel(RST_FLAG_VAL, &exynos_power->spare0); + write32(VECTOR_LOW_POWER_ADDRESS, (intptr_t)low_power_start); + write32(VECTOR_LOW_POWER_FLAG, RST_FLAG_VAL); + write32(&exynos_power->spare0, RST_FLAG_VAL); /* On next SEV, shutdown all cores. */ - writel((intptr_t)power_down_core, VECTOR_CORE_SEV_HANDLER); + write32(VECTOR_CORE_SEV_HANDLER, (intptr_t)power_down_core); /* Ask all cores in WFE mode to shutdown. */ dsb(); diff --git a/src/soc/samsung/exynos5420/spi.c b/src/soc/samsung/exynos5420/spi.c index 6ceb92edd2..3d71f79529 100644 --- a/src/soc/samsung/exynos5420/spi.c +++ b/src/soc/samsung/exynos5420/spi.c @@ -69,9 +69,9 @@ static inline struct exynos_spi_slave *to_exynos_spi(struct spi_slave *slave) static void spi_sw_reset(struct exynos_spi *regs, int word) { - const uint32_t orig_mode_cfg = readl(®s->mode_cfg); + const uint32_t orig_mode_cfg = read32(®s->mode_cfg); uint32_t mode_cfg = orig_mode_cfg; - const uint32_t orig_swap_cfg = readl(®s->swap_cfg); + const uint32_t orig_swap_cfg = read32(®s->swap_cfg); uint32_t swap_cfg = orig_swap_cfg; mode_cfg &= ~(SPI_MODE_CH_WIDTH_MASK | SPI_MODE_BUS_WIDTH_MASK); @@ -89,9 +89,9 @@ static void spi_sw_reset(struct exynos_spi *regs, int word) } if (mode_cfg != orig_mode_cfg) - writel(mode_cfg, ®s->mode_cfg); + write32(®s->mode_cfg, mode_cfg); if (swap_cfg != orig_swap_cfg) - writel(swap_cfg, ®s->swap_cfg); + write32(®s->swap_cfg, swap_cfg); clrbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); setbits_le32(®s->ch_cfg, SPI_CH_RST); @@ -106,7 +106,7 @@ void spi_init(void) static void exynos_spi_init(struct exynos_spi *regs) { // Set FB_CLK_SEL. - writel(SPI_FB_DELAY_180, ®s->fb_clk); + write32(®s->fb_clk, SPI_FB_DELAY_180); // CPOL: Active high. clrbits_le32(®s->ch_cfg, SPI_CH_CPOL_L); @@ -157,10 +157,10 @@ static void spi_transfer(struct exynos_spi *regs, void *in, const void *out, out_bytes = in_bytes = packets * width; spi_sw_reset(regs, width == 4); - writel(packets | SPI_PACKET_CNT_EN, ®s->pkt_cnt); + write32(®s->pkt_cnt, packets | SPI_PACKET_CNT_EN); while (out_bytes || in_bytes) { - uint32_t spi_sts = readl(®s->spi_sts); + uint32_t spi_sts = read32(®s->spi_sts); int rx_lvl = ((spi_sts >> 15) & 0x1ff); int tx_lvl = ((spi_sts >> 6) & 0x1ff); @@ -171,13 +171,13 @@ static void spi_transfer(struct exynos_spi *regs, void *in, const void *out, memcpy(&data, outb, width); outb += width; } - writel(data, ®s->tx_data); + write32(®s->tx_data, data); out_bytes -= width; } if (rx_lvl >= width) { - uint32_t data = readl(®s->rx_data); + uint32_t data = read32(®s->rx_data); if (inb) { memcpy(inb, &data, width); diff --git a/src/soc/samsung/exynos5420/timer.c b/src/soc/samsung/exynos5420/timer.c index 1e25771dbd..2abaf3bc5d 100644 --- a/src/soc/samsung/exynos5420/timer.c +++ b/src/soc/samsung/exynos5420/timer.c @@ -27,16 +27,15 @@ static const uint32_t clocks_per_usec = MCT_HZ/1000000; static uint64_t mct_raw_value(void) { - uint64_t upper = readl(&exynos_mct->g_cnt_u); - uint64_t lower = readl(&exynos_mct->g_cnt_l); + uint64_t upper = read32(&exynos_mct->g_cnt_u); + uint64_t lower = read32(&exynos_mct->g_cnt_l); return (upper << 32) | lower; } void init_timer(void) { - writel(readl(&exynos_mct->g_tcon) | (0x1 << 8), - &exynos_mct->g_tcon); + write32(&exynos_mct->g_tcon, read32(&exynos_mct->g_tcon) | (0x1 << 8)); } void timer_monotonic_get(struct mono_time *mt) diff --git a/src/soc/samsung/exynos5420/tmu.c b/src/soc/samsung/exynos5420/tmu.c index 8ed78bba4a..19c72fdac3 100644 --- a/src/soc/samsung/exynos5420/tmu.c +++ b/src/soc/samsung/exynos5420/tmu.c @@ -80,7 +80,7 @@ static int get_cur_temp(struct tmu_info *info) struct tmu_reg *reg = (struct tmu_reg *)info->tmu_base; /* Temperature code range between min 25 and max 125 */ - cur_temp = readl(®->current_temp) & 0xff; + cur_temp = read32(®->current_temp) & 0xff; /* Calibrate current temperature */ if (cur_temp) @@ -142,10 +142,10 @@ static void tmu_setup_parameters(struct tmu_info *info) struct tmu_reg *reg = (struct tmu_reg *)info->tmu_base; /* Must reload for using efuse value at EXYNOS */ - writel(TRIMINFO_RELOAD, ®->triminfo_control); + write32(®->triminfo_control, TRIMINFO_RELOAD); /* Get the compensation parameter */ - te_temp = readl(®->triminfo); + te_temp = read32(®->triminfo); info->te1 = te_temp & TRIM_INFO_MASK; info->te2 = ((te_temp >> 8) & TRIM_INFO_MASK); @@ -169,8 +169,8 @@ static void tmu_setup_parameters(struct tmu_info *info) (hwtrip_code << 24)); /* Set interrupt level */ - writel(rising_value, ®->threshold_temp_rise); - writel(cooling_temp, ®->threshold_temp_fall); + write32(®->threshold_temp_rise, rising_value); + write32(®->threshold_temp_fall, cooling_temp); /* * Need to init all register settings after getting parameter info @@ -183,20 +183,20 @@ static void tmu_setup_parameters(struct tmu_info *info) * TODO(bhthompson): rewrite this code such that we are not performing * a hard wipe of tmu_control and re verify functionality. */ - writel(data->slope, ®->tmu_control); + write32(®->tmu_control, data->slope); - writel(INTCLEARALL, ®->intclear); + write32(®->intclear, INTCLEARALL); /* TMU core enable */ - con = readl(®->tmu_control); + con = read32(®->tmu_control); con |= (info->tmu_mux << 20) | THERM_TRIP_EN | CORE_EN; - writel(con, ®->tmu_control); + write32(®->tmu_control, con); /* Enable HW thermal trip */ power_enable_hw_thermal_trip(); /* LEV1 LEV2 interrupt enable */ - writel(INTEN_RISE1 | INTEN_RISE2, ®->inten); + write32(®->inten, INTEN_RISE1 | INTEN_RISE2); } /* diff --git a/src/soc/samsung/exynos5420/trustzone.c b/src/soc/samsung/exynos5420/trustzone.c index 983690dbef..5712768355 100644 --- a/src/soc/samsung/exynos5420/trustzone.c +++ b/src/soc/samsung/exynos5420/trustzone.c @@ -33,10 +33,10 @@ void trustzone_init(void) for (addr = TZPC10_BASE; addr <= TZPC9_BASE; addr += TZPC_BASE_OFFSET) { tzpc = (struct exynos_tzpc *)addr; if (addr == TZPC0_BASE) - writel(R0SIZE, &tzpc->r0size); - writel(DECPROTXSET, &tzpc->decprot0set); - writel(DECPROTXSET, &tzpc->decprot1set); - writel(DECPROTXSET, &tzpc->decprot2set); - writel(DECPROTXSET, &tzpc->decprot3set); + write32(&tzpc->r0size, R0SIZE); + write32(&tzpc->decprot0set, DECPROTXSET); + write32(&tzpc->decprot1set, DECPROTXSET); + write32(&tzpc->decprot2set, DECPROTXSET); + write32(&tzpc->decprot3set, DECPROTXSET); } } diff --git a/src/soc/samsung/exynos5420/uart.c b/src/soc/samsung/exynos5420/uart.c index 74e5067b0d..bfdd54a891 100644 --- a/src/soc/samsung/exynos5420/uart.c +++ b/src/soc/samsung/exynos5420/uart.c @@ -66,7 +66,7 @@ static void serial_setbrg_dev(struct s5p_uart *uart) uclk = clock_get_periph_rate(PERIPH_ID_UART3); val = uclk / default_baudrate(); - writel(val / 16 - 1, &uart->ubrdiv); + write32(&uart->ubrdiv, val / 16 - 1); /* * FIXME(dhendrix): the original uart.h had a "br_rest" value which @@ -88,12 +88,12 @@ static void serial_setbrg_dev(struct s5p_uart *uart) static void exynos5_init_dev(struct s5p_uart *uart) { /* enable FIFOs */ - writel(0x1, &uart->ufcon); - writel(0, &uart->umcon); + write32(&uart->ufcon, 0x1); + write32(&uart->umcon, 0); /* 8N1 */ - writel(0x3, &uart->ulcon); + write32(&uart->ulcon, 0x3); /* No interrupts, no DMA, pure polling */ - writel(0x245, &uart->ucon); + write32(&uart->ucon, 0x245); serial_setbrg_dev(uart); } @@ -114,7 +114,7 @@ static int exynos5_uart_err_check(struct s5p_uart *uart, int op) else mask = 0xf; - return readl(&uart->uerstat) & mask; + return read32(&uart->uerstat) & mask; } /* @@ -125,13 +125,13 @@ static int exynos5_uart_err_check(struct s5p_uart *uart, int op) static unsigned char exynos5_uart_rx_byte(struct s5p_uart *uart) { /* wait for character to arrive */ - while (!(readl(&uart->ufstat) & (RX_FIFO_COUNT_MASK | + while (!(read32(&uart->ufstat) & (RX_FIFO_COUNT_MASK | RX_FIFO_FULL_MASK))) { if (exynos5_uart_err_check(uart, 0)) return 0; } - return readb(&uart->urxh) & 0xff; + return read8(&uart->urxh) & 0xff; } /* @@ -140,12 +140,12 @@ static unsigned char exynos5_uart_rx_byte(struct s5p_uart *uart) static void exynos5_uart_tx_byte(struct s5p_uart *uart, unsigned char data) { /* wait for room in the tx FIFO */ - while ((readl(&uart->ufstat) & TX_FIFO_FULL_MASK)) { + while ((read32(&uart->ufstat) & TX_FIFO_FULL_MASK)) { if (exynos5_uart_err_check(uart, 1)) return; } - writeb(data, &uart->utxh); + write8(&uart->utxh, data); } uintptr_t uart_platform_base(int idx) diff --git a/src/soc/samsung/exynos5420/usb.c b/src/soc/samsung/exynos5420/usb.c index 0df63e2666..9313fea147 100644 --- a/src/soc/samsung/exynos5420/usb.c +++ b/src/soc/samsung/exynos5420/usb.c @@ -57,23 +57,13 @@ static void setup_dwc3(struct exynos5_usb_drd_dwc3 *dwc3) /* Set relevant registers to default values (clearing all reset bits) */ - writel(0x1 << 24 | /* activate PHY low power states */ - 0x4 << 19 | /* low power delay value */ - 0x1 << 18 | /* activate PHY low power delay */ - 0x1 << 17 | /* enable SuperSpeed PHY suspend */ - 0x1 << 1 | /* default Tx deemphasis value */ - 0, &dwc3->usb3pipectl); + write32(&dwc3->usb3pipectl, + 0x1 << 24 | 0x4 << 19 | 0x1 << 18 | 0x1 << 17 | 0x1 << 1 | 0); /* Configure PHY clock turnaround for 8-bit UTMI+, disable suspend */ - writel(0x9 << 10 | /* PHY clock turnaround for 8-bit UTMI+ */ - 0x1 << 8 | /* enable PHY sleep in L1 */ - 0x1 << 6 | /* enable PHY suspend */ - 0, &dwc3->usb2phycfg); - - writel(0x5dc << 19 | /* suspend clock scale for 24MHz */ - 0x1 << 16 | /* retry SS three times (bugfix from U-Boot) */ - 0x1 << 12 | /* port capability HOST */ - 0, &dwc3->ctl); + write32(&dwc3->usb2phycfg, 0x9 << 10 | 0x1 << 8 | 0x1 << 6 | 0); + + write32(&dwc3->ctl, 0x5dc << 19 | 0x1 << 16 | 0x1 << 12 | 0); } void setup_usb_drd0_dwc3() @@ -96,44 +86,25 @@ static void setup_drd_phy(struct exynos5_usb_drd_phy *phy) setbits_le32(&phy->linksystem, 0x1 << 27 | 0x20 << 1); /* Disable OTG, ID0 and DRVVBUS, do not force sleep/suspend */ - writel(1 << 6, &phy->utmi); - - writel(0x88 << 23 | /* spread spectrum refclk selector */ - 0x1 << 20 | /* enable spread spectrum */ - 0x1 << 19 | /* enable prescaler refclk */ - 0x68 << 11 | /* multiplier for 24MHz refclk */ - 0x5 << 5 | /* select 24MHz refclk (weird, from U-Boot) */ - 0x1 << 4 | /* power supply in normal operating mode */ - 0x3 << 2 | /* use external refclk (undocumented on 5420?)*/ - 0x1 << 1 | /* force port reset */ - 0x1 << 0 | /* normal operating mode */ - 0, &phy->clkrst); - - writel(0x9 << 26 | /* LOS level */ - 0x3 << 22 | /* TX VREF tune */ - 0x1 << 20 | /* TX rise tune */ - 0x1 << 18 | /* TX res tune */ - 0x3 << 13 | /* TX HS X Vtune */ - 0x3 << 9 | /* TX FS/LS tune */ - 0x3 << 6 | /* SQRX tune */ - 0x4 << 3 | /* OTG tune */ - 0x4 << 0 | /* comp disc tune */ - 0, &phy->param0); - - writel(0x7f << 19 | /* reserved */ - 0x7f << 12 | /* Tx launch amplitude */ - 0x20 << 6 | /* Tx deemphasis 6dB */ - 0x1c << 0 | /* Tx deemphasis 3.5dB (value from U-Boot) */ - 0, &phy->param1); + write32(&phy->utmi, 1 << 6); + + write32(&phy->clkrst, + 0x88 << 23 | 0x1 << 20 | 0x1 << 19 | 0x68 << 11 | 0x5 << 5 | 0x1 << 4 | 0x3 << 2 | 0x1 << 1 | 0x1 << 0 | 0); + + write32(&phy->param0, + 0x9 << 26 | 0x3 << 22 | 0x1 << 20 | 0x1 << 18 | 0x3 << 13 | 0x3 << 9 | 0x3 << 6 | 0x4 << 3 | 0x4 << 0 | 0); + + write32(&phy->param1, + 0x7f << 19 | 0x7f << 12 | 0x20 << 6 | 0x1c << 0 | 0); /* disable all test features */ - writel(0, &phy->test); + write32(&phy->test, 0); /* UTMI clock select? ("must be 0x1") */ - writel(0x1 << 2, &phy->utmiclksel); + write32(&phy->utmiclksel, 0x1 << 2); /* Samsung magic, undocumented (from U-Boot) */ - writel(0x0, &phy->resume); + write32(&phy->resume, 0x0); udelay(10); clrbits_le32(&phy->clkrst, 0x1 << 1); /* deassert port reset */ @@ -163,7 +134,7 @@ void setup_usb_host_phy(int hsic_gpio) printk(BIOS_DEBUG, "Powering up USB HOST PHY (%s HSIC)\n", hsic_gpio ? "with" : "without"); - hostphy_ctrl0 = readl(&exynos_usb_host_phy->usbphyctrl0); + hostphy_ctrl0 = read32(&exynos_usb_host_phy->usbphyctrl0); hostphy_ctrl0 &= ~(HOST_CTRL0_FSEL_MASK | HOST_CTRL0_COMMONON_N | /* HOST Phy setting */ @@ -177,7 +148,7 @@ void setup_usb_host_phy(int hsic_gpio) /* HOST Phy setting */ HOST_CTRL0_LINKSWRST | HOST_CTRL0_UTMISWRST); - writel(hostphy_ctrl0, &exynos_usb_host_phy->usbphyctrl0); + write32(&exynos_usb_host_phy->usbphyctrl0, hostphy_ctrl0); udelay(10); clrbits_le32(&exynos_usb_host_phy->usbphyctrl0, HOST_CTRL0_LINKSWRST | -- cgit v1.2.3