From 1b296ee3b832bc9dbff57c680a3de509db3c95fd Mon Sep 17 00:00:00 2001
From: Elyes HAOUAS <ehaouas@noos.fr>
Date: Wed, 19 Feb 2020 20:48:29 +0100
Subject: soc/{samsung,sifive}: Fix typos

Change-Id: Ib370f04a63160e2a8a1b06620e659feb45c8f552
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
---
 src/soc/samsung/exynos5420/spi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/soc/samsung/exynos5420')

diff --git a/src/soc/samsung/exynos5420/spi.c b/src/soc/samsung/exynos5420/spi.c
index a98f51d72c..ec9002399b 100644
--- a/src/soc/samsung/exynos5420/spi.c
+++ b/src/soc/samsung/exynos5420/spi.c
@@ -101,7 +101,7 @@ static void exynos_spi_init(struct exynos_spi *regs)
 	// CPOL: Active high.
 	clrbits32(&regs->ch_cfg, SPI_CH_CPOL_L);
 
-	// Clear rx and tx channel if set priveously.
+	// Clear rx and tx channel if set previously.
 	clrbits32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON);
 
 	setbits32(&regs->swap_cfg,
-- 
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