From 1fc2ba5e6d85f3c7eef00a7e6b0b3ee1352fbfa9 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sun, 7 Dec 2014 14:59:11 -0700 Subject: samsung/exynos5420: Spelling Fixes Change-Id: I966645c83ae78943a7dbb9dc05af4fded6f4e5b5 Signed-off-by: Martin Roth Reviewed-on: http://review.coreboot.org/7703 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan --- src/soc/samsung/exynos5420/dmc_common.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/soc/samsung/exynos5420/dmc_common.c') diff --git a/src/soc/samsung/exynos5420/dmc_common.c b/src/soc/samsung/exynos5420/dmc_common.c index 433312eb3e..e651b7f947 100644 --- a/src/soc/samsung/exynos5420/dmc_common.c +++ b/src/soc/samsung/exynos5420/dmc_common.c @@ -63,7 +63,7 @@ int dmc_config_zq(struct mem_timings *mem, val &= ~ZQ_MANUAL_STR; /* - * Since we are manaully calibrating the ZQ values, + * Since we are manually calibrating the ZQ values, * we are looping for the ZQ_init to complete. */ i = ZQ_INIT_TIMEOUT; @@ -96,12 +96,12 @@ void update_reset_dll(struct exynos5_dmc *dmc, enum ddr_mode mode) writel(val, &dmc->phycontrol0); } - /* Update DLL Information: Force DLL Resyncronization */ + /* Update DLL Information: Force DLL Resynchronization */ val = readl(&dmc->phycontrol0); val |= FP_RSYNC; writel(val, &dmc->phycontrol0); - /* Reset Force DLL Resyncronization */ + /* Reset Force DLL Resynchronization */ val = readl(&dmc->phycontrol0); val &= ~FP_RSYNC; writel(val, &dmc->phycontrol0); -- cgit v1.2.3