From 55009af42c39f413c49503670ce9bc2858974962 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Mon, 2 Dec 2019 22:03:27 -0800 Subject: Change all clrsetbits_leXX() to clrsetbitsXX() This patch changes all existing instances of clrsetbits_leXX() to the new endian-independent clrsetbitsXX(), after double-checking that they're all in SoC-specific code operating on CPU registers and not actually trying to make an endian conversion. This patch was created by running sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g' across the codebase and cleaning up formatting a bit. Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin --- src/soc/samsung/exynos5420/clock_init.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'src/soc/samsung/exynos5420/clock_init.c') diff --git a/src/soc/samsung/exynos5420/clock_init.c b/src/soc/samsung/exynos5420/clock_init.c index eae08a8dea..92abf32081 100644 --- a/src/soc/samsung/exynos5420/clock_init.c +++ b/src/soc/samsung/exynos5420/clock_init.c @@ -42,7 +42,7 @@ void system_clock_init(void) write32(&exynos_clock->kpll_lock, KPLL_LOCK_VAL); write32(&exynos_clock->rpll_lock, RPLL_LOCK_VAL); - setbits_le32(&exynos_clock->clk_src_cpu, MUX_HPM_SEL_MASK); + setbits32(&exynos_clock->clk_src_cpu, MUX_HPM_SEL_MASK); write32(&exynos_clock->clk_src_top6, 0); @@ -52,7 +52,7 @@ void system_clock_init(void) write32(&exynos_clock->clk_div_cpu0, CLK_DIV_CPU0_VAL); /* switch A15 clock source to OSC clock before changing APLL */ - clrbits_le32(&exynos_clock->clk_src_cpu, APLL_FOUT); + clrbits32(&exynos_clock->clk_src_cpu, APLL_FOUT); /* Set APLL */ write32(&exynos_clock->apll_con1, APLL_CON1_VAL); @@ -62,13 +62,13 @@ void system_clock_init(void) ; /* now it is safe to switch to APLL */ - setbits_le32(&exynos_clock->clk_src_cpu, APLL_FOUT); + setbits32(&exynos_clock->clk_src_cpu, APLL_FOUT); write32(&exynos_clock->clk_src_kfc, SRC_KFC_HPM_SEL); write32(&exynos_clock->clk_div_kfc0, CLK_DIV_KFC_VAL); /* switch A7 clock source to OSC clock before changing KPLL */ - clrbits_le32(&exynos_clock->clk_src_kfc, KPLL_FOUT); + clrbits32(&exynos_clock->clk_src_kfc, KPLL_FOUT); /* Set KPLL*/ write32(&exynos_clock->kpll_con1, KPLL_CON1_VAL); @@ -78,7 +78,7 @@ void system_clock_init(void) ; /* now it is safe to switch to KPLL */ - setbits_le32(&exynos_clock->clk_src_kfc, KPLL_FOUT); + setbits32(&exynos_clock->clk_src_kfc, KPLL_FOUT); /* Set MPLL */ write32(&exynos_clock->mpll_con1, MPLL_CON1_VAL); -- cgit v1.2.3