From 55009af42c39f413c49503670ce9bc2858974962 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Mon, 2 Dec 2019 22:03:27 -0800 Subject: Change all clrsetbits_leXX() to clrsetbitsXX() This patch changes all existing instances of clrsetbits_leXX() to the new endian-independent clrsetbitsXX(), after double-checking that they're all in SoC-specific code operating on CPU registers and not actually trying to make an endian conversion. This patch was created by running sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g' across the codebase and cleaning up formatting a bit. Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin --- src/soc/samsung/exynos5250/clock.c | 8 +- src/soc/samsung/exynos5250/clock_init.c | 248 ++++++++++++++++---------------- src/soc/samsung/exynos5250/dp-reg.c | 20 +-- src/soc/samsung/exynos5250/fb.c | 24 ++-- src/soc/samsung/exynos5250/power.c | 12 +- src/soc/samsung/exynos5250/spi.c | 34 ++--- src/soc/samsung/exynos5250/usb.c | 40 +++--- 7 files changed, 193 insertions(+), 193 deletions(-) (limited to 'src/soc/samsung/exynos5250') diff --git a/src/soc/samsung/exynos5250/clock.c b/src/soc/samsung/exynos5250/clock.c index efb0de31f3..e762af1908 100644 --- a/src/soc/samsung/exynos5250/clock.c +++ b/src/soc/samsung/exynos5250/clock.c @@ -425,7 +425,7 @@ void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned int divisor) periph_id); return; } - clrsetbits_le32(reg, mask << shift, (divisor & mask) << shift); + clrsetbits32(reg, mask << shift, (divisor & mask) << shift); } void clock_ll_set_ratio(enum periph_id periph_id, unsigned int divisor) @@ -460,7 +460,7 @@ void clock_ll_set_ratio(enum periph_id periph_id, unsigned int divisor) periph_id); return; } - clrsetbits_le32(reg, mask << shift, (divisor & mask) << shift); + clrsetbits32(reg, mask << shift, (divisor & mask) << shift); } /** @@ -644,7 +644,7 @@ int clock_epll_set_rate(unsigned long rate) void clock_select_i2s_clk_source(void) { - clrsetbits_le32(&exynos_clock->src_peric1, AUDIO1_SEL_MASK, + clrsetbits32(&exynos_clock->src_peric1, AUDIO1_SEL_MASK, (CLK_SRC_SCLK_EPLL)); } @@ -664,7 +664,7 @@ int clock_set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq) printk(BIOS_DEBUG, "src frq = %d des frq = %d ", src_frq, dst_frq); return -1; } - clrsetbits_le32(&exynos_clock->div_peric4, AUDIO_1_RATIO_MASK, + clrsetbits32(&exynos_clock->div_peric4, AUDIO_1_RATIO_MASK, (div & AUDIO_1_RATIO_MASK)); return 0; } diff --git a/src/soc/samsung/exynos5250/clock_init.c b/src/soc/samsung/exynos5250/clock_init.c index fa19eb1763..ca3dbd9921 100644 --- a/src/soc/samsung/exynos5250/clock_init.c +++ b/src/soc/samsung/exynos5250/clock_init.c @@ -28,27 +28,27 @@ void system_clock_init(struct mem_timings *mem, /* Turn on the MCT as early as possible. */ exynos_mct->g_tcon |= (1 << 8); - clrbits_le32(&exynos_clock->src_cpu, MUX_APLL_SEL_MASK); + clrbits32(&exynos_clock->src_cpu, MUX_APLL_SEL_MASK); do { val = read32(&exynos_clock->mux_stat_cpu); } while ((val | MUX_APLL_SEL_MASK) != val); - clrbits_le32(&exynos_clock->src_core1, MUX_MPLL_SEL_MASK); + clrbits32(&exynos_clock->src_core1, MUX_MPLL_SEL_MASK); do { val = read32(&exynos_clock->mux_stat_core1); } while ((val | MUX_MPLL_SEL_MASK) != val); - clrbits_le32(&exynos_clock->src_top2, MUX_CPLL_SEL_MASK); - clrbits_le32(&exynos_clock->src_top2, MUX_EPLL_SEL_MASK); - clrbits_le32(&exynos_clock->src_top2, MUX_VPLL_SEL_MASK); - clrbits_le32(&exynos_clock->src_top2, MUX_GPLL_SEL_MASK); + clrbits32(&exynos_clock->src_top2, MUX_CPLL_SEL_MASK); + clrbits32(&exynos_clock->src_top2, MUX_EPLL_SEL_MASK); + clrbits32(&exynos_clock->src_top2, MUX_VPLL_SEL_MASK); + clrbits32(&exynos_clock->src_top2, MUX_GPLL_SEL_MASK); tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK | MUX_GPLL_SEL_MASK; do { val = read32(&exynos_clock->mux_stat_top2); } while ((val | tmp) != val); - clrbits_le32(&exynos_clock->src_cdrex, MUX_BPLL_SEL_MASK); + clrbits32(&exynos_clock->src_cdrex, MUX_BPLL_SEL_MASK); do { val = read32(&exynos_clock->mux_stat_cdrex); } while ((val | MUX_BPLL_SEL_MASK) != val); @@ -94,7 +94,7 @@ void system_clock_init(struct mem_timings *mem, } while (0 != val); /* switch A15 clock source to OSC clock before changing APLL */ - clrbits_le32(&exynos_clock->src_cpu, APLL_FOUT); + clrbits32(&exynos_clock->src_cpu, APLL_FOUT); /* Set APLL */ write32(&exynos_clock->apll_con1, APLL_CON1_VAL); @@ -105,7 +105,7 @@ void system_clock_init(struct mem_timings *mem, ; /* now it is safe to switch to APLL */ - setbits_le32(&exynos_clock->src_cpu, APLL_FOUT); + setbits32(&exynos_clock->src_cpu, APLL_FOUT); /* Set MPLL */ write32(&exynos_clock->mpll_con1, MPLL_CON1_VAL); @@ -118,7 +118,7 @@ void system_clock_init(struct mem_timings *mem, * Configure MUX_MPLL_FOUT to choose the direct clock source * path and avoid the fixed DIV/2 block to save power */ - setbits_le32(&exynos_clock->pll_div2_sel, MUX_MPLL_FOUT_SEL); + setbits32(&exynos_clock->pll_div2_sel, MUX_MPLL_FOUT_SEL); /* Set BPLL */ if (mem->use_bpll) { @@ -128,7 +128,7 @@ void system_clock_init(struct mem_timings *mem, while ((read32(&exynos_clock->bpll_con0) & BPLL_CON0_LOCKED) == 0) ; - setbits_le32(&exynos_clock->pll_div2_sel, MUX_BPLL_FOUT_SEL); + setbits32(&exynos_clock->pll_div2_sel, MUX_BPLL_FOUT_SEL); } /* Set CPLL */ @@ -280,124 +280,124 @@ void system_clock_init(struct mem_timings *mem, void clock_gate(void) { /* CLK_GATE_IP_SYSRGT */ - clrbits_le32(&exynos_clock->gate_ip_sysrgt, CLK_C2C_MASK); + clrbits32(&exynos_clock->gate_ip_sysrgt, CLK_C2C_MASK); /* CLK_GATE_IP_ACP */ - clrbits_le32(&exynos_clock->gate_ip_acp, CLK_SMMUG2D_MASK | - CLK_SMMUSSS_MASK | - CLK_SMMUMDMA_MASK | - CLK_ID_REMAPPER_MASK | - CLK_G2D_MASK | - CLK_SSS_MASK | - CLK_MDMA_MASK | - CLK_SECJTAG_MASK); + clrbits32(&exynos_clock->gate_ip_acp, CLK_SMMUG2D_MASK | + CLK_SMMUSSS_MASK | + CLK_SMMUMDMA_MASK | + CLK_ID_REMAPPER_MASK | + CLK_G2D_MASK | + CLK_SSS_MASK | + CLK_MDMA_MASK | + CLK_SECJTAG_MASK); /* CLK_GATE_BUS_SYSLFT */ - clrbits_le32(&exynos_clock->gate_bus_syslft, CLK_EFCLK_MASK); + clrbits32(&exynos_clock->gate_bus_syslft, CLK_EFCLK_MASK); /* CLK_GATE_IP_ISP0 */ - clrbits_le32(&exynos_clock->gate_ip_isp0, CLK_UART_ISP_MASK | - CLK_WDT_ISP_MASK | - CLK_PWM_ISP_MASK | - CLK_MTCADC_ISP_MASK | - CLK_I2C1_ISP_MASK | - CLK_I2C0_ISP_MASK | - CLK_MPWM_ISP_MASK | - CLK_MCUCTL_ISP_MASK | - CLK_INT_COMB_ISP_MASK | - CLK_SMMU_MCUISP_MASK | - CLK_SMMU_SCALERP_MASK | - CLK_SMMU_SCALERC_MASK | - CLK_SMMU_FD_MASK | - CLK_SMMU_DRC_MASK | - CLK_SMMU_ISP_MASK | - CLK_GICISP_MASK | - CLK_ARM9S_MASK | - CLK_MCUISP_MASK | - CLK_SCALERP_MASK | - CLK_SCALERC_MASK | - CLK_FD_MASK | - CLK_DRC_MASK | - CLK_ISP_MASK); + clrbits32(&exynos_clock->gate_ip_isp0, CLK_UART_ISP_MASK | + CLK_WDT_ISP_MASK | + CLK_PWM_ISP_MASK | + CLK_MTCADC_ISP_MASK | + CLK_I2C1_ISP_MASK | + CLK_I2C0_ISP_MASK | + CLK_MPWM_ISP_MASK | + CLK_MCUCTL_ISP_MASK | + CLK_INT_COMB_ISP_MASK | + CLK_SMMU_MCUISP_MASK | + CLK_SMMU_SCALERP_MASK | + CLK_SMMU_SCALERC_MASK | + CLK_SMMU_FD_MASK | + CLK_SMMU_DRC_MASK | + CLK_SMMU_ISP_MASK | + CLK_GICISP_MASK | + CLK_ARM9S_MASK | + CLK_MCUISP_MASK | + CLK_SCALERP_MASK | + CLK_SCALERC_MASK | + CLK_FD_MASK | + CLK_DRC_MASK | + CLK_ISP_MASK); /* CLK_GATE_IP_ISP1 */ - clrbits_le32(&exynos_clock->gate_ip_isp1, CLK_SPI1_ISP_MASK | - CLK_SPI0_ISP_MASK | - CLK_SMMU3DNR_MASK | - CLK_SMMUDIS1_MASK | - CLK_SMMUDIS0_MASK | - CLK_SMMUODC_MASK | - CLK_3DNR_MASK | - CLK_DIS_MASK | - CLK_ODC_MASK); + clrbits32(&exynos_clock->gate_ip_isp1, CLK_SPI1_ISP_MASK | + CLK_SPI0_ISP_MASK | + CLK_SMMU3DNR_MASK | + CLK_SMMUDIS1_MASK | + CLK_SMMUDIS0_MASK | + CLK_SMMUODC_MASK | + CLK_3DNR_MASK | + CLK_DIS_MASK | + CLK_ODC_MASK); /* CLK_GATE_SCLK_ISP */ - clrbits_le32(&exynos_clock->gate_sclk_isp, SCLK_MPWM_ISP_MASK); + clrbits32(&exynos_clock->gate_sclk_isp, SCLK_MPWM_ISP_MASK); /* CLK_GATE_IP_GSCL */ - clrbits_le32(&exynos_clock->gate_ip_gscl, CLK_SMMUFIMC_LITE2_MASK | - CLK_SMMUFIMC_LITE1_MASK | - CLK_SMMUFIMC_LITE0_MASK | - CLK_SMMUGSCL3_MASK | - CLK_SMMUGSCL2_MASK | - CLK_SMMUGSCL1_MASK | - CLK_SMMUGSCL0_MASK | - CLK_GSCL_WRAP_B_MASK | - CLK_GSCL_WRAP_A_MASK | - CLK_CAMIF_TOP_MASK | - CLK_GSCL3_MASK | - CLK_GSCL2_MASK | - CLK_GSCL1_MASK | - CLK_GSCL0_MASK); + clrbits32(&exynos_clock->gate_ip_gscl, CLK_SMMUFIMC_LITE2_MASK | + CLK_SMMUFIMC_LITE1_MASK | + CLK_SMMUFIMC_LITE0_MASK | + CLK_SMMUGSCL3_MASK | + CLK_SMMUGSCL2_MASK | + CLK_SMMUGSCL1_MASK | + CLK_SMMUGSCL0_MASK | + CLK_GSCL_WRAP_B_MASK | + CLK_GSCL_WRAP_A_MASK | + CLK_CAMIF_TOP_MASK | + CLK_GSCL3_MASK | + CLK_GSCL2_MASK | + CLK_GSCL1_MASK | + CLK_GSCL0_MASK); /* CLK_GATE_IP_DISP1 */ - clrbits_le32(&exynos_clock->gate_ip_disp1, CLK_SMMUTVX_MASK | - CLK_ASYNCTVX_MASK | - CLK_HDMI_MASK | - CLK_MIXER_MASK | - CLK_DSIM1_MASK); + clrbits32(&exynos_clock->gate_ip_disp1, CLK_SMMUTVX_MASK | + CLK_ASYNCTVX_MASK | + CLK_HDMI_MASK | + CLK_MIXER_MASK | + CLK_DSIM1_MASK); /* CLK_GATE_IP_MFC */ - clrbits_le32(&exynos_clock->gate_ip_mfc, CLK_SMMUMFCR_MASK | - CLK_SMMUMFCL_MASK | - CLK_MFC_MASK); + clrbits32(&exynos_clock->gate_ip_mfc, CLK_SMMUMFCR_MASK | + CLK_SMMUMFCL_MASK | + CLK_MFC_MASK); /* CLK_GATE_IP_GEN */ - clrbits_le32(&exynos_clock->gate_ip_gen, CLK_SMMUMDMA1_MASK | - CLK_SMMUJPEG_MASK | - CLK_SMMUROTATOR_MASK | - CLK_MDMA1_MASK | - CLK_JPEG_MASK | - CLK_ROTATOR_MASK); + clrbits32(&exynos_clock->gate_ip_gen, CLK_SMMUMDMA1_MASK | + CLK_SMMUJPEG_MASK | + CLK_SMMUROTATOR_MASK | + CLK_MDMA1_MASK | + CLK_JPEG_MASK | + CLK_ROTATOR_MASK); /* CLK_GATE_IP_FSYS */ - clrbits_le32(&exynos_clock->gate_ip_fsys, CLK_WDT_IOP_MASK | - CLK_SMMUMCU_IOP_MASK | - CLK_SATA_PHY_I2C_MASK | - CLK_SATA_PHY_CTRL_MASK | - CLK_MCUCTL_MASK | - CLK_NFCON_MASK | - CLK_SMMURTIC_MASK | - CLK_RTIC_MASK | - CLK_MIPI_HSI_MASK | - CLK_USBOTG_MASK | - CLK_SATA_MASK | - CLK_PDMA1_MASK | - CLK_PDMA0_MASK | - CLK_MCU_IOP_MASK); + clrbits32(&exynos_clock->gate_ip_fsys, CLK_WDT_IOP_MASK | + CLK_SMMUMCU_IOP_MASK | + CLK_SATA_PHY_I2C_MASK | + CLK_SATA_PHY_CTRL_MASK | + CLK_MCUCTL_MASK | + CLK_NFCON_MASK | + CLK_SMMURTIC_MASK | + CLK_RTIC_MASK | + CLK_MIPI_HSI_MASK | + CLK_USBOTG_MASK | + CLK_SATA_MASK | + CLK_PDMA1_MASK | + CLK_PDMA0_MASK | + CLK_MCU_IOP_MASK); /* CLK_GATE_IP_PERIC */ - clrbits_le32(&exynos_clock->gate_ip_peric, CLK_HS_I2C3_MASK | - CLK_HS_I2C2_MASK | - CLK_HS_I2C1_MASK | - CLK_HS_I2C0_MASK | - CLK_AC97_MASK | - CLK_SPDIF_MASK | - CLK_PCM2_MASK | - CLK_PCM1_MASK | - CLK_I2S2_MASK | - CLK_SPI2_MASK | - CLK_SPI0_MASK); + clrbits32(&exynos_clock->gate_ip_peric, CLK_HS_I2C3_MASK | + CLK_HS_I2C2_MASK | + CLK_HS_I2C1_MASK | + CLK_HS_I2C0_MASK | + CLK_AC97_MASK | + CLK_SPDIF_MASK | + CLK_PCM2_MASK | + CLK_PCM1_MASK | + CLK_I2S2_MASK | + CLK_SPI2_MASK | + CLK_SPI0_MASK); /* * CLK_GATE_IP_PERIS @@ -405,33 +405,33 @@ void clock_gate(void) * register (PRO_ID) works correctly when the OS kernel determines * which chip it is running on. */ - clrbits_le32(&exynos_clock->gate_ip_peris, CLK_RTC_MASK | - CLK_TZPC9_MASK | - CLK_TZPC8_MASK | - CLK_TZPC7_MASK | - CLK_TZPC6_MASK | - CLK_TZPC5_MASK | - CLK_TZPC4_MASK | - CLK_TZPC3_MASK | - CLK_TZPC2_MASK | - CLK_TZPC1_MASK | - CLK_TZPC0_MASK); + clrbits32(&exynos_clock->gate_ip_peris, CLK_RTC_MASK | + CLK_TZPC9_MASK | + CLK_TZPC8_MASK | + CLK_TZPC7_MASK | + CLK_TZPC6_MASK | + CLK_TZPC5_MASK | + CLK_TZPC4_MASK | + CLK_TZPC3_MASK | + CLK_TZPC2_MASK | + CLK_TZPC1_MASK | + CLK_TZPC0_MASK); /* CLK_GATE_BLOCK */ - clrbits_le32(&exynos_clock->gate_block, CLK_ACP_MASK); + clrbits32(&exynos_clock->gate_block, CLK_ACP_MASK); /* CLK_GATE_IP_CDREX */ - clrbits_le32(&exynos_clock->gate_ip_cdrex, CLK_DPHY0_MASK | - CLK_DPHY1_MASK | - CLK_TZASC_DRBXR_MASK); + clrbits32(&exynos_clock->gate_ip_cdrex, CLK_DPHY0_MASK | + CLK_DPHY1_MASK | + CLK_TZASC_DRBXR_MASK); } void clock_init_dp_clock(void) { /* DP clock enable */ - setbits_le32(&exynos_clock->gate_ip_disp1, CLK_GATE_DP1_ALLOW); + setbits32(&exynos_clock->gate_ip_disp1, CLK_GATE_DP1_ALLOW); /* We run DP at 267 Mhz */ - setbits_le32(&exynos_clock->div_disp1_0, CLK_DIV_DISP1_0_FIMD1); + setbits32(&exynos_clock->div_disp1_0, CLK_DIV_DISP1_0_FIMD1); } diff --git a/src/soc/samsung/exynos5250/dp-reg.c b/src/soc/samsung/exynos5250/dp-reg.c index e57b0af2f9..fa5e11cf2a 100644 --- a/src/soc/samsung/exynos5250/dp-reg.c +++ b/src/soc/samsung/exynos5250/dp-reg.c @@ -34,8 +34,8 @@ void s5p_dp_reset(struct s5p_dp_device *dp) write32(&base->dp_tx_sw_reset, RESET_DP_TX); /* Stop Video */ - clrbits_le32(&base->video_ctl_1, VIDEO_EN); - clrbits_le32(&base->video_ctl_1, HDCP_VIDEO_MUTE); + clrbits32(&base->video_ctl_1, VIDEO_EN); + clrbits32(&base->video_ctl_1, HDCP_VIDEO_MUTE); reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N | AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N | @@ -124,12 +124,12 @@ int s5p_dp_init_analog_func(struct s5p_dp_device *dp) reg = PLL_LOCK_CHG; write32(&base->common_int_sta_1, reg); - clrbits_le32(&base->dp_debug_ctl, (F_PLL_LOCK | PLL_LOCK_CTRL)); + clrbits32(&base->dp_debug_ctl, (F_PLL_LOCK | PLL_LOCK_CTRL)); /* Power up PLL */ if (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { - clrbits_le32(&base->dp_pll_ctl, DP_PLL_PD); + clrbits32(&base->dp_pll_ctl, DP_PLL_PD); stopwatch_init_msecs_expire(&sw, PLL_LOCK_TIMEOUT); @@ -143,7 +143,7 @@ int s5p_dp_init_analog_func(struct s5p_dp_device *dp) } /* Enable Serdes FIFO function and Link symbol clock domain module */ - clrbits_le32(&base->func_en_2, (SERDES_FIFO_FUNC_EN_N | + clrbits32(&base->func_en_2, (SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N | AUX_FUNC_EN_N)); return 0; } @@ -158,7 +158,7 @@ void s5p_dp_init_aux(struct s5p_dp_device *dp) write32(&base->dp_int_sta, reg); /* Disable AUX channel module */ - setbits_le32(&base->func_en_2, AUX_FUNC_EN_N); + setbits32(&base->func_en_2, AUX_FUNC_EN_N); /* Disable AUX transaction H/W retry */ reg = (3 & AUX_BIT_PERIOD_MASK) << AUX_BIT_PERIOD_SHIFT; @@ -172,7 +172,7 @@ void s5p_dp_init_aux(struct s5p_dp_device *dp) write32(&base->aux_ch_defer_dtl, reg); /* Enable AUX channel module */ - clrbits_le32(&base->func_en_2, AUX_FUNC_EN_N); + clrbits32(&base->func_en_2, AUX_FUNC_EN_N); } int s5p_dp_start_aux_transaction(struct s5p_dp_device *dp) @@ -181,7 +181,7 @@ int s5p_dp_start_aux_transaction(struct s5p_dp_device *dp) struct exynos5_dp *base = dp->base; /* Enable AUX CH operation */ - setbits_le32(&base->aux_ch_ctl_2, AUX_EN); + setbits32(&base->aux_ch_ctl_2, AUX_EN); /* Is AUX CH command reply received? */ reg = read32(&base->dp_int_sta); @@ -386,7 +386,7 @@ void s5p_dp_set_video_cr_mn(struct s5p_dp_device *dp, struct exynos5_dp *base = dp->base; if (type == REGISTER_M) { - setbits_le32(&base->sys_ctl_4, FIX_M_VID); + setbits32(&base->sys_ctl_4, FIX_M_VID); reg = m_value >> M_VID_0_VALUE_SHIFT; write32(&base->m_vid_0, reg); @@ -406,7 +406,7 @@ void s5p_dp_set_video_cr_mn(struct s5p_dp_device *dp, reg = (n_value >> N_VID_2_VALUE_SHIFT); write32(&base->n_vid_2, reg); } else { - clrbits_le32(&base->sys_ctl_4, FIX_M_VID); + clrbits32(&base->sys_ctl_4, FIX_M_VID); write32(&base->n_vid_0, 0x00); write32(&base->n_vid_1, 0x80); diff --git a/src/soc/samsung/exynos5250/fb.c b/src/soc/samsung/exynos5250/fb.c index 64980a1aec..2e8acf2688 100644 --- a/src/soc/samsung/exynos5250/fb.c +++ b/src/soc/samsung/exynos5250/fb.c @@ -100,7 +100,7 @@ short console_row; /* Bypass FIMD of DISP1_BLK */ static void fimd_bypass(void) { - setbits_le32(&exynos_sysreg->disp1blk_cfg, FIMDBYPASS_DISP1); + setbits32(&exynos_sysreg->disp1blk_cfg, FIMDBYPASS_DISP1); exynos_sysreg->disp1blk_cfg &= ~FIMDBYPASS_DISP1; } @@ -145,7 +145,7 @@ void fb_init(unsigned long int fb_size, void *lcdbase, write32(&exynos_fimd->vidosd0b, val); write32(&exynos_fimd->vidosd0c, pd->xres * pd->yres); - setbits_le32(&exynos_fimd->shadowcon, CHANNEL0_EN); + setbits32(&exynos_fimd->shadowcon, CHANNEL0_EN); val = BPPMODE_F_RGB_16BIT_565 << BPPMODE_F_OFFSET; val |= ENWIN_F_ENABLE | HALF_WORD_SWAP_EN; @@ -159,7 +159,7 @@ void fb_init(unsigned long int fb_size, void *lcdbase, void exynos_fimd_disable(void) { write32(&exynos_fimd->wincon0, 0); - clrbits_le32(&exynos_fimd->shadowcon, CHANNEL0_EN); + clrbits32(&exynos_fimd->shadowcon, CHANNEL0_EN); } #endif @@ -205,16 +205,16 @@ static int s5p_dp_config_video(struct s5p_dp_device *dp, /* Set to use the register calculated M/N video */ s5p_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0); - clrbits_le32(&base->video_ctl_10, FORMAT_SEL); + clrbits32(&base->video_ctl_10, FORMAT_SEL); /* Disable video mute */ - clrbits_le32(&base->video_ctl_1, HDCP_VIDEO_MUTE); + clrbits32(&base->video_ctl_1, HDCP_VIDEO_MUTE); /* Configure video slave mode */ s5p_dp_enable_video_master(dp); /* Enable video */ - setbits_le32(&base->video_ctl_1, VIDEO_EN); + setbits32(&base->video_ctl_1, VIDEO_EN); timeout = s5p_dp_is_video_stream_on(dp); if (timeout) { @@ -258,7 +258,7 @@ static int s5p_dp_enable_scramble(struct s5p_dp_device *dp) u8 data; struct exynos5_dp *base = dp->base; - clrbits_le32(&base->dp_training_ptn_set, SCRAMBLING_DISABLE); + clrbits32(&base->dp_training_ptn_set, SCRAMBLING_DISABLE); if (s5p_dp_read_byte_from_dpcd(dp, DPCD_ADDR_TRAINING_PATTERN_SET, &data)) { @@ -288,7 +288,7 @@ static int s5p_dp_init_dp(struct s5p_dp_device *dp) s5p_dp_reset(dp); /* SW defined function Normal operation */ - clrbits_le32(&base->func_en_1, SW_FUNC_EN_N); + clrbits32(&base->func_en_1, SW_FUNC_EN_N); ret = s5p_dp_init_analog_func(dp); if (!ret) @@ -397,7 +397,7 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, struct exynos5_dp *base = dp->base; /* Stop Video */ - clrbits_le32(&base->video_ctl_1, VIDEO_EN); + clrbits32(&base->video_ctl_1, VIDEO_EN); stopwatch_init_msecs_expire(&sw, PLL_LOCK_TIMEOUT); @@ -411,12 +411,12 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, printk(BIOS_SPEW, "PLL is %slocked\n", pll_is_locked == PLL_LOCKED ? "": "not "); /* Reset Macro */ - setbits_le32(&base->dp_phy_test, MACRO_RST); + setbits32(&base->dp_phy_test, MACRO_RST); /* 10 us is the minimum reset time. */ udelay(10); - clrbits_le32(&base->dp_phy_test, MACRO_RST); + clrbits32(&base->dp_phy_test, MACRO_RST); /* Set TX pre-emphasis to minimum */ for (lane = 0; lane < max_lane; lane++) @@ -534,7 +534,7 @@ int dp_controller_init(struct s5p_dp_device *dp_device) base = dp->base; /* Enable enhanced mode */ - setbits_le32(&base->sys_ctl_4, ENHANCED); + setbits32(&base->sys_ctl_4, ENHANCED); write32(&base->lane_count_set, dp->link_train.lane_count); write32(&base->link_bw_set, dp->link_train.link_rate); diff --git a/src/soc/samsung/exynos5250/power.c b/src/soc/samsung/exynos5250/power.c index e649e949c8..37369b3482 100644 --- a/src/soc/samsung/exynos5250/power.c +++ b/src/soc/samsung/exynos5250/power.c @@ -26,7 +26,7 @@ static void ps_hold_setup(void) { /* Set PS-Hold high */ - setbits_le32(&exynos_power->ps_hold_ctrl, + setbits32(&exynos_power->ps_hold_ctrl, POWER_PS_HOLD_CONTROL_DATA_HIGH); } @@ -35,7 +35,7 @@ void power_reset(void) /* Clear inform1 so there's no change we think we've got a wake reset */ exynos_power->inform1 = 0; - setbits_le32(&exynos_power->sw_reset, 1); + setbits32(&exynos_power->sw_reset, 1); } void do_board_reset(void) @@ -46,7 +46,7 @@ void do_board_reset(void) /* This function never returns */ void power_shutdown(void) { - clrbits_le32(&exynos_power->ps_hold_ctrl, + clrbits32(&exynos_power->ps_hold_ctrl, POWER_PS_HOLD_CONTROL_DATA_HIGH); halt(); @@ -54,13 +54,13 @@ void power_shutdown(void) void power_enable_dp_phy(void) { - setbits_le32(&exynos_power->dptx_phy_control, EXYNOS_DP_PHY_ENABLE); + setbits32(&exynos_power->dptx_phy_control, EXYNOS_DP_PHY_ENABLE); } void power_enable_hw_thermal_trip(void) { /* Enable HW thermal trip */ - setbits_le32(&exynos_power->ps_hold_ctrl, POWER_ENABLE_HW_TRIP); + setbits32(&exynos_power->ps_hold_ctrl, POWER_ENABLE_HW_TRIP); } uint32_t power_read_reset_status(void) @@ -84,7 +84,7 @@ int power_init(void) void power_enable_xclkout(void) { /* use xxti for xclk out */ - clrsetbits_le32(&exynos_power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK, + clrsetbits32(&exynos_power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK, PMU_DEBUG_XXTI); } diff --git a/src/soc/samsung/exynos5250/spi.c b/src/soc/samsung/exynos5250/spi.c index e35f888177..4d5e01f493 100644 --- a/src/soc/samsung/exynos5250/spi.c +++ b/src/soc/samsung/exynos5250/spi.c @@ -42,8 +42,8 @@ static void exynos_spi_rx_tx(struct exynos_spi *regs, int todo, ASSERT(todo % 4 == 0); out_bytes = in_bytes = todo; - setbits_le32(®s->ch_cfg, SPI_CH_RST); - clrbits_le32(®s->ch_cfg, SPI_CH_RST); + setbits32(®s->ch_cfg, SPI_CH_RST); + clrbits32(®s->ch_cfg, SPI_CH_RST); write32(®s->pkt_cnt, ((todo * 8) / 32) | SPI_PACKET_CNT_EN); while (in_bytes) { @@ -81,22 +81,22 @@ int exynos_spi_open(struct exynos_spi *regs) /* set FB_CLK_SEL */ write32(®s->fb_clk, SPI_FB_DELAY_180); /* set CH_WIDTH and BUS_WIDTH as word */ - setbits_le32(®s->mode_cfg, + setbits32(®s->mode_cfg, SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD); - clrbits_le32(®s->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */ + clrbits32(®s->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */ /* clear rx and tx channel if set previously */ - clrbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); + clrbits32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); - setbits_le32(®s->swap_cfg, - SPI_RX_SWAP_EN | SPI_RX_BYTE_SWAP | SPI_RX_HWORD_SWAP); + setbits32(®s->swap_cfg, + SPI_RX_SWAP_EN | SPI_RX_BYTE_SWAP | SPI_RX_HWORD_SWAP); /* do a soft reset */ - setbits_le32(®s->ch_cfg, SPI_CH_RST); - clrbits_le32(®s->ch_cfg, SPI_CH_RST); + setbits32(®s->ch_cfg, SPI_CH_RST); + clrbits32(®s->ch_cfg, SPI_CH_RST); /* now set rx and tx channel ON */ - setbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN); + setbits32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN); return 0; } @@ -104,7 +104,7 @@ int exynos_spi_read(struct exynos_spi *regs, void *dest, u32 len, u32 off) { int upto, todo; int i; - clrbits_le32(®s->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */ + clrbits32(®s->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */ /* Send read instruction (0x3h) followed by a 24 bit addr */ write32(®s->tx_data, (SF_READ_DATA_CMD << 24) | off); @@ -117,7 +117,7 @@ int exynos_spi_read(struct exynos_spi *regs, void *dest, u32 len, u32 off) exynos_spi_rx_tx(regs, todo, dest, (void *)(off), i); } - setbits_le32(®s->cs_reg, SPI_SLAVE_SIG_INACT);/* make the CS high */ + setbits32(®s->cs_reg, SPI_SLAVE_SIG_INACT);/* make the CS high */ return len; } @@ -128,17 +128,17 @@ int exynos_spi_close(struct exynos_spi *regs) * Let put controller mode to BYTE as * SPI driver does not support WORD mode yet */ - clrbits_le32(®s->mode_cfg, - SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD); + clrbits32(®s->mode_cfg, + SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD); write32(®s->swap_cfg, 0); /* * Flush spi tx, rx fifos and reset the SPI controller * and clear rx/tx channel */ - clrsetbits_le32(®s->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST); - clrbits_le32(®s->ch_cfg, SPI_CH_RST); - clrbits_le32(®s->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON); + clrsetbits32(®s->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST); + clrbits32(®s->ch_cfg, SPI_CH_RST); + clrbits32(®s->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON); return 0; } diff --git a/src/soc/samsung/exynos5250/usb.c b/src/soc/samsung/exynos5250/usb.c index 076e42eee9..12b658aef3 100644 --- a/src/soc/samsung/exynos5250/usb.c +++ b/src/soc/samsung/exynos5250/usb.c @@ -25,9 +25,9 @@ static void reset_dwc3(struct exynos5_usb_drd_dwc3 *dwc3) { - setbits_le32(&dwc3->ctl, 0x1 << 11); /* core soft reset */ - setbits_le32(&dwc3->usb3pipectl, 0x1 << 31); /* PHY soft reset */ - setbits_le32(&dwc3->usb2phycfg, 0x1 << 31); /* PHY soft reset */ + setbits32(&dwc3->ctl, 0x1 << 11); /* core soft reset */ + setbits32(&dwc3->usb3pipectl, 0x1 << 31); /* PHY soft reset */ + setbits32(&dwc3->usb2phycfg, 0x1 << 31); /* PHY soft reset */ } void reset_usb_drd_dwc3() @@ -77,7 +77,7 @@ static void setup_drd_phy(struct exynos5_usb_drd_phy *phy) /* Set all PHY registers to default values */ /* XHCI Version 1.0, Frame Length adjustment 30 MHz */ - setbits_le32(&phy->linksystem, 0x1 << 27 | 0x20 << 1); + setbits32(&phy->linksystem, 0x1 << 27 | 0x20 << 1); /* Disable OTG, ID0 and DRVVBUS, do not force sleep/suspend */ write32(&phy->utmi, 1 << 6); @@ -120,13 +120,13 @@ static void setup_drd_phy(struct exynos5_usb_drd_phy *phy) write32(&phy->resume, 0x0); udelay(10); - clrbits_le32(&phy->clkrst, 0x1 << 1); /* deassert port reset */ + clrbits32(&phy->clkrst, 0x1 << 1); /* deassert port reset */ } void setup_usb_drd_phy() { printk(BIOS_DEBUG, "Powering up USB DRD PHY\n"); - setbits_le32(&exynos_power->usb_drd_phy_ctrl, POWER_USB_PHY_CTRL_EN); + setbits32(&exynos_power->usb_drd_phy_ctrl, POWER_USB_PHY_CTRL_EN); setup_drd_phy(exynos_usb_drd_phy); } @@ -134,8 +134,8 @@ void setup_usb_host_phy(int hsic_gpio) { unsigned int hostphy_ctrl0; - setbits_le32(&exynos_sysreg->usb20_phy_cfg, USB20_PHY_CFG_EN); - setbits_le32(&exynos_power->usb_host_phy_ctrl, POWER_USB_PHY_CTRL_EN); + setbits32(&exynos_sysreg->usb20_phy_cfg, USB20_PHY_CFG_EN); + setbits32(&exynos_power->usb_host_phy_ctrl, POWER_USB_PHY_CTRL_EN); printk(BIOS_DEBUG, "Powering up USB HOST PHY (%s HSIC)\n", hsic_gpio ? "with" : "without"); @@ -156,13 +156,13 @@ void setup_usb_host_phy(int hsic_gpio) HOST_CTRL0_UTMISWRST); write32(&exynos_usb_host_phy->usbphyctrl0, hostphy_ctrl0); udelay(10); - clrbits_le32(&exynos_usb_host_phy->usbphyctrl0, - HOST_CTRL0_LINKSWRST | - HOST_CTRL0_UTMISWRST); + clrbits32(&exynos_usb_host_phy->usbphyctrl0, + HOST_CTRL0_LINKSWRST | + HOST_CTRL0_UTMISWRST); udelay(20); /* EHCI Ctrl setting */ - setbits_le32(&exynos_usb_host_phy->ehcictrl, + setbits32(&exynos_usb_host_phy->ehcictrl, EHCICTRL_ENAINCRXALIGN | EHCICTRL_ENAINCR4 | EHCICTRL_ENAINCR8 | @@ -175,15 +175,15 @@ void setup_usb_host_phy(int hsic_gpio) gpio_direction_output(hsic_gpio, 1); udelay(5000); - clrbits_le32(&exynos_usb_host_phy->hsicphyctrl1, - HOST_CTRL0_SIDDQ | - HOST_CTRL0_FORCESLEEP | - HOST_CTRL0_FORCESUSPEND); - setbits_le32(&exynos_usb_host_phy->hsicphyctrl1, - HOST_CTRL0_PHYSWRST); + clrbits32(&exynos_usb_host_phy->hsicphyctrl1, + HOST_CTRL0_SIDDQ | + HOST_CTRL0_FORCESLEEP | + HOST_CTRL0_FORCESUSPEND); + setbits32(&exynos_usb_host_phy->hsicphyctrl1, + HOST_CTRL0_PHYSWRST); udelay(10); - clrbits_le32(&exynos_usb_host_phy->hsicphyctrl1, - HOST_CTRL0_PHYSWRST); + clrbits32(&exynos_usb_host_phy->hsicphyctrl1, + HOST_CTRL0_PHYSWRST); } /* At this point we need to wait for 50ms before talking to -- cgit v1.2.3