From 2f37bd65518865688b9234afce0d467508d6f465 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Thu, 19 Feb 2015 14:51:15 -0800 Subject: arm(64): Globally replace writel(v, a) with write32(a, v) This patch is a raw application of the following spatch to src/: @@ expression A, V; @@ - writel(V, A) + write32(A, V) @@ expression A, V; @@ - writew(V, A) + write16(A, V) @@ expression A, V; @@ - writeb(V, A) + write8(A, V) @@ expression A; @@ - readl(A) + read32(A) @@ expression A; @@ - readb(A) + read8(A) BRANCH=none BUG=chromium:444723 TEST=None (depends on next patch) Change-Id: I5dd96490c85ee2bcbc669f08bc6fff0ecc0f9e27 Signed-off-by: Patrick Georgi Original-Commit-Id: 64f643da95d85954c4d4ea91c34a5c69b9b08eb6 Original-Change-Id: I366a2eb5b3a0df2279ebcce572fe814894791c42 Original-Signed-off-by: Julius Werner Original-Reviewed-on: https://chromium-review.googlesource.com/254864 Reviewed-on: http://review.coreboot.org/9836 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/samsung/exynos5250/dmc_common.c | 50 ++++++++++++++++----------------- 1 file changed, 25 insertions(+), 25 deletions(-) (limited to 'src/soc/samsung/exynos5250/dmc_common.c') diff --git a/src/soc/samsung/exynos5250/dmc_common.c b/src/soc/samsung/exynos5250/dmc_common.c index 17dff1ec92..2e64905d9d 100644 --- a/src/soc/samsung/exynos5250/dmc_common.c +++ b/src/soc/samsung/exynos5250/dmc_common.c @@ -45,19 +45,19 @@ int dmc_config_zq(struct mem_timings *mem, val |= mem->zq_mode_dds << PHY_CON16_ZQ_MODE_DDS_SHIFT; val |= mem->zq_mode_term << PHY_CON16_ZQ_MODE_TERM_SHIFT; val |= ZQ_CLK_DIV_EN; - writel(val, &phy0_ctrl->phy_con16); - writel(val, &phy1_ctrl->phy_con16); + write32(&phy0_ctrl->phy_con16, val); + write32(&phy1_ctrl->phy_con16, val); /* Disable termination */ if (mem->zq_mode_noterm) val |= PHY_CON16_ZQ_MODE_NOTERM_MASK; - writel(val, &phy0_ctrl->phy_con16); - writel(val, &phy1_ctrl->phy_con16); + write32(&phy0_ctrl->phy_con16, val); + write32(&phy1_ctrl->phy_con16, val); /* ZQ_MANUAL_START: Enable */ val |= ZQ_MANUAL_STR; - writel(val, &phy0_ctrl->phy_con16); - writel(val, &phy1_ctrl->phy_con16); + write32(&phy0_ctrl->phy_con16, val); + write32(&phy1_ctrl->phy_con16, val); /* ZQ_MANUAL_START: Disable */ val &= ~ZQ_MANUAL_STR; @@ -67,22 +67,22 @@ int dmc_config_zq(struct mem_timings *mem, * we are looping for the ZQ_init to complete. */ i = ZQ_INIT_TIMEOUT; - while ((readl(&phy0_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) { + while ((read32(&phy0_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) { udelay(1); i--; } if (!i) return -1; - writel(val, &phy0_ctrl->phy_con16); + write32(&phy0_ctrl->phy_con16, val); i = ZQ_INIT_TIMEOUT; - while ((readl(&phy1_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) { + while ((read32(&phy1_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) { udelay(1); i--; } if (!i) return -1; - writel(val, &phy1_ctrl->phy_con16); + write32(&phy1_ctrl->phy_con16, val); return 0; } @@ -93,18 +93,18 @@ void update_reset_dll(struct exynos5_dmc *dmc, enum ddr_mode mode) if (mode == DDR_MODE_DDR3) { val = MEM_TERM_EN | PHY_TERM_EN | DMC_CTRL_SHGATE; - writel(val, &dmc->phycontrol0); + write32(&dmc->phycontrol0, val); } /* Update DLL Information: Force DLL Resynchronization */ - val = readl(&dmc->phycontrol0); + val = read32(&dmc->phycontrol0); val |= FP_RSYNC; - writel(val, &dmc->phycontrol0); + write32(&dmc->phycontrol0, val); /* Reset Force DLL Resynchronization */ - val = readl(&dmc->phycontrol0); + val = read32(&dmc->phycontrol0); val &= ~FP_RSYNC; - writel(val, &dmc->phycontrol0); + write32(&dmc->phycontrol0, val); } void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc) @@ -121,7 +121,7 @@ void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc) mask |= chip << DIRECT_CMD_CHIP_SHIFT; /* Sending NOP command */ - writel(DIRECT_CMD_NOP | mask, &dmc->directcmd); + write32(&dmc->directcmd, DIRECT_CMD_NOP | mask); /* * TODO(alim.akhtar@samsung.com): Do we need these @@ -132,15 +132,15 @@ void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc) /* Sending EMRS/MRS commands */ for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) { - writel(mem->direct_cmd_msr[i] | mask, - &dmc->directcmd); + write32(&dmc->directcmd, + mem->direct_cmd_msr[i] | mask); udelay(100); } if (mem->send_zq_init) { /* Sending ZQINIT command */ - writel(DIRECT_CMD_ZQINIT | mask, - &dmc->directcmd); + write32(&dmc->directcmd, + DIRECT_CMD_ZQINIT | mask); /* * FIXME: This was originally sdelay(10000) * in the imported u-boot code. That may have @@ -166,7 +166,7 @@ void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc) mask |= chip << DIRECT_CMD_CHIP_SHIFT; /* PALL (all banks precharge) CMD */ - writel(DIRECT_CMD_PALL | mask, &dmc->directcmd); + write32(&dmc->directcmd, DIRECT_CMD_PALL | mask); udelay(100); } } @@ -174,8 +174,8 @@ void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc) void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc) { - writel(mem->memconfig, &dmc->memconfig0); - writel(mem->memconfig, &dmc->memconfig1); - writel(DMC_MEMBASECONFIG0_VAL, &dmc->membaseconfig0); - writel(DMC_MEMBASECONFIG1_VAL, &dmc->membaseconfig1); + write32(&dmc->memconfig0, mem->memconfig); + write32(&dmc->memconfig1, mem->memconfig); + write32(&dmc->membaseconfig0, DMC_MEMBASECONFIG0_VAL); + write32(&dmc->membaseconfig1, DMC_MEMBASECONFIG1_VAL); } -- cgit v1.2.3